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Searched refs:VirtReg (Results 1 – 25 of 85) sorted by relevance

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/external/llvm/lib/CodeGen/
DLiveRegMatrix.cpp97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
100 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
101 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit, in assign()
106 Matrix[Unit].unify(VirtReg, Range); in assign()
114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument
115 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign()
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
118 VRM->clearVirt(VirtReg.reg); in unassign()
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DRegAllocBase.cpp85 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
86 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
89 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
90 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
91 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
92 LIS->removeInterval(VirtReg->reg); in allocatePhysRegs()
103 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
104 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); in allocatePhysRegs()
107 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
114 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
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DRegAllocGreedy.cpp212 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
213 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
216 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
218 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
357 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
362 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
373 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
378 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
383 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
494 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument
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DRegAllocFast.cpp71 unsigned VirtReg; // Virtual register number. member
77 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){} in LiveReg()
80 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
171 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
176 void killVirtReg(unsigned VirtReg);
178 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
184 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg() argument
185 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
187 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { in findLiveVirtReg()
188 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
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DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify() argument
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract() argument
67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { in isSeenInterference()
106 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg); in isSeenInterference()
130 if (VirtReg->empty() || LiveUnion->empty()) { in collectInterferingVRegs()
136 VirtRegI = VirtReg->begin(); in collectInterferingVRegs()
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DRegAllocBasic.cpp102 unsigned selectOrSplit(LiveInterval &VirtReg,
111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
174 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences()
180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) in spillInterferences()
186 " interferences with " << VirtReg << "\n"); in spillInterferences()
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument
226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix); in selectOrSplit()
229 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
248 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) in selectOrSplit()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign()
107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
113 Matrix[Unit].unify(VirtReg, Range); in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument
122 Register PhysReg = VRM->getPhys(VirtReg.reg); in unassign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " in unassign()
125 VRM->clearVirt(VirtReg.reg); in unassign()
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DRegAllocFast.cpp86 Register VirtReg; ///< Virtual register number. member
91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
94 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
193 void killVirtReg(Register VirtReg);
195 void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg);
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg() argument
204 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
207 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
208 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
213 MCPhysReg defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
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DRegAllocBase.cpp89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
90 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
93 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
95 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
96 LIS->removeInterval(VirtReg->reg); in allocatePhysRegs()
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) in allocatePhysRegs()
108 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); in allocatePhysRegs()
113 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
120 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); in allocatePhysRegs()
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DRegAllocBasic.cpp103 unsigned selectOrSplit(LiveInterval &VirtReg,
117 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
144 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) { in INITIALIZE_PASS_DEPENDENCY()
145 LiveInterval &LI = LIS->getInterval(VirtReg); in INITIALIZE_PASS_DEPENDENCY()
146 if (VRM->hasPhys(VirtReg)) { in INITIALIZE_PASS_DEPENDENCY()
159 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
160 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
164 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
204 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
212 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences()
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DRegAllocGreedy.cpp255 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
256 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
259 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
261 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
465 unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg);
469 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
473 LiveInterval &VirtReg, SlotIndex Start,
477 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
489 unsigned isSplitBenefitWorthCost(LiveInterval &VirtReg);
491 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
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DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify() argument
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract() argument
67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { in isSeenInterference()
105 return is_contained(InterferingVRegs, VirtReg); in isSeenInterference()
/external/llvm-project/llvm/lib/CodeGen/
DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) { in assign() argument
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to " in assign()
107 assert(!VRM->hasPhys(VirtReg.reg()) && "Duplicate VirtReg assignment"); in assign()
108 VRM->assignVirt2Phys(VirtReg.reg(), PhysReg); in assign()
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { in assign()
113 Matrix[Unit].unify(VirtReg, Range); in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument
122 Register PhysReg = VRM->getPhys(VirtReg.reg()); in unassign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI) in unassign()
125 VRM->clearVirt(VirtReg.reg()); in unassign()
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DRegAllocFast.cpp90 Register VirtReg; ///< Virtual register number. member
96 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
99 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
228 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg() argument
229 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
232 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
233 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
240 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
243 Register VirtReg);
244 void defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
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DRegAllocBase.cpp89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
90 assert(!VRM->hasPhys(VirtReg->reg()) && "Register already assigned"); in allocatePhysRegs()
93 if (MRI->reg_nodbg_empty(VirtReg->reg())) { in allocatePhysRegs()
94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
95 aboutToRemoveInterval(*VirtReg); in allocatePhysRegs()
96 LIS->removeInterval(VirtReg->reg()); in allocatePhysRegs()
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
108 << ':' << *VirtReg << " w=" << VirtReg->weight() << '\n'); in allocatePhysRegs()
113 MCRegister AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
120 I = MRI->reg_instr_begin(VirtReg->reg()), in allocatePhysRegs()
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DRegAllocBasic.cpp103 MCRegister selectOrSplit(LiveInterval &VirtReg,
122 bool spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg,
149 bool RABasic::LRE_CanEraseVirtReg(Register VirtReg) { in INITIALIZE_PASS_DEPENDENCY()
150 LiveInterval &LI = LIS->getInterval(VirtReg); in INITIALIZE_PASS_DEPENDENCY()
151 if (VRM->hasPhys(VirtReg)) { in INITIALIZE_PASS_DEPENDENCY()
164 void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg() argument
165 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
169 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
209 bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg, in spillInterferences() argument
217 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences()
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DRegAllocGreedy.cpp250 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
251 return ExtraRegInfo[VirtReg.reg()].Stage; in getStage()
254 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
256 ExtraRegInfo[VirtReg.reg()].Stage = Stage; in setStage()
466 Register canReassign(LiveInterval &VirtReg, Register PrevReg);
470 bool canEvictInterferenceInRange(LiveInterval &VirtReg, MCRegister PhysReg,
474 LiveInterval &VirtReg, SlotIndex Start,
478 bool mayRecolorAllInterferences(MCRegister PhysReg, LiveInterval &VirtReg,
491 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
497 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
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DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify() argument
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract() argument
67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); in extract()
104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { in isSeenInterference()
105 return is_contained(InterferingVRegs, VirtReg); in isSeenInterference()
/external/llvm/include/llvm/CodeGen/
DLiveIntervalUnion.h87 void unify(LiveInterval &VirtReg, const LiveRange &Range);
88 void unify(LiveInterval &VirtReg) { in unify() argument
89 unify(VirtReg, VirtReg); in unify()
93 void extract(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg) { in extract() argument
95 extract(VirtReg, VirtReg); in extract()
113 LiveInterval *VirtReg; variable
123 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {} in Query()
126 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query()
132 VirtReg = nullptr; in clear()
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DLiveRegMatrix.h103 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
108 void assign(LiveInterval &VirtReg, unsigned PhysReg);
113 void unassign(LiveInterval &VirtReg);
128 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
133 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
DVirtRegMap.h130 bool hasPreferredPhys(unsigned VirtReg);
135 bool hasKnownPreference(unsigned VirtReg);
151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument
152 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal()
153 return Orig ? Orig : VirtReg; in getOriginal()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DLiveRegMatrix.h107 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
119 void assign(LiveInterval &VirtReg, unsigned PhysReg);
124 void unassign(LiveInterval &VirtReg);
139 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
144 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
DVirtRegMap.h127 bool hasPreferredPhys(Register VirtReg);
132 bool hasKnownPreference(Register VirtReg);
148 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument
149 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal()
150 return Orig ? Orig : VirtReg; in getOriginal()
/external/llvm-project/llvm/include/llvm/CodeGen/
DLiveRegMatrix.h107 InterferenceKind checkInterference(LiveInterval &VirtReg, MCRegister PhysReg);
119 void assign(LiveInterval &VirtReg, MCRegister PhysReg);
124 void unassign(LiveInterval &VirtReg);
139 bool checkRegMaskInterference(LiveInterval &VirtReg,
145 bool checkRegUnitInterference(LiveInterval &VirtReg, MCRegister PhysReg);
DVirtRegMap.h126 bool hasPreferredPhys(Register VirtReg);
131 bool hasKnownPreference(Register VirtReg);
147 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument
148 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal()
149 return Orig ? Orig : VirtReg; in getOriginal()

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