Home
last modified time | relevance | path

Searched refs:ZeroReg (Results 1 – 25 of 60) sorted by relevance

123

/external/llvm-project/llvm/tools/llvm-exegesis/lib/Mips/
DTarget.cpp74 unsigned ZeroReg; in loadImmediate() local
77 ZeroReg = Mips::ZERO; in loadImmediate()
82 ZeroReg = Mips::ZERO_64; in loadImmediate()
91 .addReg(ZeroReg) in loadImmediate()
104 .addReg(ZeroReg) in loadImmediate()
123 .addReg(ZeroReg) in loadImmediate()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupSetCC.cpp105 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
110 ZeroReg); in runOnMachineFunction()
116 .addReg(ZeroReg) in runOnMachineFunction()
DX86FlagsCopyLowering.cpp1054 Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass); in rewriteSetCarryExtended() local
1055 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOV32r0), ZeroReg); in rewriteSetCarryExtended()
1056 ZeroReg = AdjustReg(ZeroReg); in rewriteSetCarryExtended()
1081 .addReg(ZeroReg) in rewriteSetCarryExtended()
/external/llvm-project/llvm/lib/Target/X86/
DX86FixupSetCC.cpp114 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
116 ZeroReg); in runOnMachineFunction()
122 .addReg(ZeroReg) in runOnMachineFunction()
/external/llvm/lib/Target/X86/
DX86FixupSetCC.cpp163 unsigned ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
168 ZeroReg); in runOnMachineFunction()
174 .addReg(ZeroReg) in runOnMachineFunction()
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX8664.cpp373 Variable *ZeroReg = RebasePtr; in _sandbox_mem_reference() local
392 assert(ZeroReg == Base || AbsoluteAddress || isAssignedToRspOrRbp(Base)); in _sandbox_mem_reference()
396 ZeroReg = Base; in _sandbox_mem_reference()
408 ZeroReg = Base; in _sandbox_mem_reference()
427 if (Shift == 0 && isAssignedToRspOrRbp(Index) && ZeroReg == RebasePtr) { in _sandbox_mem_reference()
428 ZeroReg = Index; in _sandbox_mem_reference()
455 if (Base != nullptr && Base != ZeroReg) in _sandbox_mem_reference()
457 if (Index != nullptr && Index != ZeroReg) in _sandbox_mem_reference()
518 Func, Mem->getType(), ZeroReg, Offset, T, Shift, in _sandbox_mem_reference()
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/
DTargetTest.cpp46 const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64; in IsLoadLow16BitImm() local
49 ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value))); in IsLoadLow16BitImm()
/external/llvm-project/llvm/lib/Target/Mips/
DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
DMipsSEInstrInfo.cpp87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
95 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
182 if (ZeroReg) in copyPhysReg()
183 MIB.addReg(ZeroReg); in copyPhysReg()
DMipsSEISelDAGToDAG.cpp85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
93 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
99 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
119 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
122 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.cpp89 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
96 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
101 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
121 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
124 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
DMipsSEInstrInfo.cpp83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
178 if (ZeroReg) in copyPhysReg()
179 MIB.addReg(ZeroReg); in copyPhysReg()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp2851 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
2870 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
2880 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
2881 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
3438 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
3443 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
3450 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
3466 .addReg(ZeroReg) in genAlternativeCodeSequence()
3482 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
3486 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
DAArch64ExpandPseudoInsts.cpp57 unsigned ExtendImm, unsigned ZeroReg,
599 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
634 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
551 putConstant(I, ZeroReg, 0); in selectCmp()
556 ZeroReg)) in selectCmp()
562 RHSReg, ZeroReg)) in selectCmp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp2480 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
2495 MIB.addReg(ZeroReg); in copyGPRRegTuple()
3669 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
3688 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
3698 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
3699 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
3759 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
3761 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
4414 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
4419 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
DAArch64ExpandPseudoInsts.cpp73 unsigned ExtendImm, unsigned ZeroReg,
176 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
209 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
DAArch64InstrInfo.h145 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
553 putConstant(I, ZeroReg, 0); in selectCmp()
558 ZeroReg)) in selectCmp()
564 RHSReg, ZeroReg)) in selectCmp()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp2745 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
2760 MIB.addReg(ZeroReg); in copyGPRRegTuple()
4045 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4064 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
4074 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
4075 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
4135 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
4137 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
4790 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
4795 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp2169 unsigned ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2189 SrcReg = ZeroReg; in loadImmediate()
2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2236 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2265 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
3033 unsigned ZeroReg; in expandDiv() local
3037 ZeroReg = Mips::ZERO_64; in expandDiv()
3040 ZeroReg = Mips::ZERO; in expandDiv()
3051 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
3068 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDiv()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h798 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
802 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
808 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()

123