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Searched refs:addiw (Results 1 – 25 of 50) sorted by relevance

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/external/llvm-project/llvm/test/MC/RISCV/
Drv64i-aliases-valid.s35 # CHECK-EXPAND: addiw a1, a1, -2048
40 # CHECK-EXPAND: addiw a1, a1, -2047
43 # CHECK-EXPAND: addiw a1, a1, 2047
46 # CHECK-EXPAND: addiw a1, a1, -1
49 # CHECK-EXPAND: addiw a1, a1, 1
56 # CHECK-EXPAND: addiw a2, a2, 1
59 # CHECK-EXPAND: addiw a2, a2, -1
62 # CHECK-EXPAND: addiw a2, a2, -1
65 # CHECK-EXPAND: addiw a2, a2, 1
90 # CHECK-EXPAND: addiw t2, t2, -1329
[all …]
Drv64c-aliases-valid.s23 # CHECK-EXPAND: addiw a1, a1, -2048
28 # CHECK-EXPAND: addiw a1, a1, -2047
31 # CHECK-EXPAND: addiw a1, a1, 2047
34 # CHECK-EXPAND: c.addiw a1, -1
37 # CHECK-EXPAND: c.addiw a1, 1
44 # CHECK-EXPAND: c.addiw a2, 1
47 # CHECK-EXPAND: c.addiw a2, -1
50 # CHECK-EXPAND: c.addiw a2, -1
53 # CHECK-EXPAND: c.addiw a2, 1
78 # CHECK-EXPAND: addiw t2, t2, -1329
[all …]
Drv64c-invalid.s21 c.addiw t0, -33 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
22 c.addiw t0, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
23 c.addiw t0, foo # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32, 31]
24 c.addiw t0, %lo(foo) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32,…
25 c.addiw t0, %hi(foo) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-32,…
Drv64c-valid.s47 # CHECK-ASM-AND-OBJ: c.addiw a3, -32
51 c.addiw a3, -32
52 # CHECK-ASM-AND-OBJ: c.addiw a3, 31
56 c.addiw a3, 31
Dcompress-rv64i.s27 # CHEACK-ALIAS: addiw tp, tp, 31
28 # CHECK-INST: c.addiw tp, 31
30 addiw tp, tp, 31 label
Drv64i-valid.s58 # CHECK-ASM-AND-OBJ: addiw t3, t4, -2048
60 addiw x28, x29, -2048 label
61 # CHECK-ASM-AND-OBJ: addiw t5, t6, 2047
63 addiw x30, x31, 2047 label
Drv64i-invalid.s10 addiw a0, a1, -2049 # CHECK: :[[@LINE]]:15: error: operand must be a symbol with %lo/%pcrel_lo/%tpr… label
20 addiw a0, a1, %hi(foo) # CHECK: :[[@LINE]]:15: error: operand must be a symbol with %lo/%pcrel_lo/%… label
/external/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz2 ... zero 120 1cc: 1b 00 10 00 addiw zero,zero,1 121 1d0: 1 ...
/external/llvm-project/llvm/test/CodeGen/RISCV/
Drv64Zbp.ll14 ; RV64I-NEXT: addiw a2, a2, -1365
20 ; RV64I-NEXT: addiw a3, a3, 1365
50 ; RV64I-NEXT: addiw a2, a2, -1365
60 ; RV64I-NEXT: addiw a3, a3, 1365
95 ; RV64I-NEXT: addiw a2, a2, -819
101 ; RV64I-NEXT: addiw a3, a3, 819
131 ; RV64I-NEXT: addiw a2, a2, -819
141 ; RV64I-NEXT: addiw a3, a3, 819
176 ; RV64I-NEXT: addiw a2, a2, -1366
180 ; RV64I-NEXT: addiw a3, a3, 1365
[all …]
Daddimm-mulimm.ll21 ; RV64IM-NEXT: addiw a0, a0, 407
43 ; RV64IM-NEXT: addiw a1, a1, 1701
66 ; RV64IM-NEXT: addiw a1, a1, 585
86 ; RV64IM-NEXT: addiw a1, a1, -1709
89 ; RV64IM-NEXT: addiw a1, a1, -1891
Dimm.ll62 ; RV64I-NEXT: addiw a0, a0, -1297
77 ; RV64I-NEXT: addiw a0, a0, -273
120 ; RV64I-NEXT: addiw a0, a0, -64
137 ; RV64I-NEXT: addiw a0, a0, -1
154 ; RV64I-NEXT: addiw a0, a0, 580
249 ; RV64I-NEXT: addiw a0, a0, -1329
288 ; RV64I-NEXT: addiw a0, a0, -1875
326 ; RV64I-NEXT: addiw a0, a0, 1
342 ; RV64I-NEXT: addiw a0, a0, 1
359 ; RV64I-NEXT: addiw a0, a0, 1
[all …]
Drv64Zbb.ll245 ; RV64I-NEXT: addiw a2, a2, 1365
255 ; RV64I-NEXT: addiw a1, a1, 819
269 ; RV64I-NEXT: addiw a1, a1, 241
278 ; RV64I-NEXT: addiw a1, a1, 257
331 ; RV64I-NEXT: addiw a2, a2, 1365
341 ; RV64I-NEXT: addiw a1, a1, 819
355 ; RV64I-NEXT: addiw a1, a1, 241
364 ; RV64I-NEXT: addiw a1, a1, 257
406 ; RV64I-NEXT: addiw a2, a2, 1365
416 ; RV64I-NEXT: addiw a1, a1, 819
[all …]
Drv64-large-stack.ll13 ; CHECK-NEXT: addiw a0, a0, 1505
20 ; CHECK-NEXT: addiw a0, a0, 1505
Dsrem-lkk.ll51 ; RV64IM-NEXT: addiw a1, a1, -733
111 ; RV64IM-NEXT: addiw a1, a1, -31
168 ; RV64IM-NEXT: addiw a1, a1, 2045
221 ; RV64I-NEXT: addiw a1, a1, 1595
231 ; RV64IM-NEXT: addiw a1, a1, 999
243 ; RV64IM-NEXT: addiw a2, a2, 1595
314 ; RV64IM-NEXT: addiw a2, a2, -733
423 ; RV64I-NEXT: addiw a2, a2, -1
437 ; RV64IM-NEXT: addiw a2, a2, -1
486 ; RV64IM-NEXT: addiw a1, a1, -251
Dfloat-bitmanip-dagcombines.ll65 ; RV64I-NEXT: addiw a1, a1, -1
72 ; RV64IF-NEXT: addiw a1, a1, -1
111 ; RV64I-NEXT: addiw a2, a2, -1
Dsrem-vector-lkk.ll157 ; RV64IM-NEXT: addiw a5, a5, -733
173 ; RV64IM-NEXT: addiw a2, a2, -1057
189 ; RV64IM-NEXT: addiw a4, a4, -251
204 ; RV64IM-NEXT: addiw a4, a4, 1977
366 ; RV64IM-NEXT: addiw a5, a5, -733
612 ; RV64IM-NEXT: addiw a5, a5, -733
762 ; RV64I-NEXT: addiw a5, a6, -64
767 ; RV64I-NEXT: addiw a4, a6, -32
772 ; RV64I-NEXT: addiw a2, a6, -8
796 ; RV64IM-NEXT: addiw a5, a5, -733
[all …]
Dhalf-bitmanip-dagcombines.ll63 ; RV64I-NEXT: addiw a1, a1, -1
118 ; RV64I-NEXT: addiw a1, a1, -1
123 ; RV64I-NEXT: addiw a2, a2, -1
Dadd-imm.ll66 ; RV64I-NEXT: addiw a1, a1, -1
130 ; RV64I-NEXT: addiw a1, a1, -1
196 ; RV64I-NEXT: addiw a4, a4, -1096
Dalu16.ll56 ; RV64I-NEXT: addiw a1, a1, -1
133 ; RV64I-NEXT: addiw a1, a1, -64
236 ; RV64I-NEXT: addiw a2, a2, -1
272 ; RV64I-NEXT: addiw a2, a2, -1
Dstack-realignment.ll341 ; RV64I-NEXT: addiw a0, a0, -2048
346 ; RV64I-NEXT: addiw a0, a0, -1024
416 ; RV64I-NEXT: addiw a0, a0, 16
424 ; RV64I-NEXT: addiw a0, a0, -2048
427 ; RV64I-NEXT: addiw a0, a0, 16
496 ; RV64I-NEXT: addiw a0, a0, -2032
507 ; RV64I-NEXT: addiw a0, a0, -2032
Durem-vector-lkk.ll152 ; RV64IM-NEXT: addiw a5, a5, -733
169 ; RV64IM-NEXT: addiw a5, a5, 1057
183 ; RV64IM-NEXT: addiw a5, a5, -251
196 ; RV64IM-NEXT: addiw a4, a4, -1977
356 ; RV64IM-NEXT: addiw a5, a5, -733
602 ; RV64IM-NEXT: addiw a5, a5, -733
749 ; RV64IM-NEXT: addiw a5, a5, -733
869 ; RV64I-NEXT: addiw a1, a0, 1327
890 ; RV64IM-NEXT: addiw a4, a4, -1781
907 ; RV64IM-NEXT: addiw a5, a5, 1265
[all …]
Durem-lkk.ll53 ; RV64IM-NEXT: addiw a1, a1, -733
113 ; RV64IM-NEXT: addiw a1, a1, -1793
195 ; RV64IM-NEXT: addiw a1, a1, -733
285 ; RV64IM-NEXT: addiw a2, a2, -251
Dadd-before-shl.ll42 ; RV64I-NEXT: addiw a1, a1, -1
65 ; RV64I-NEXT: addiw a1, a1, -1
Dcopysign-casts.ll189 ; RV64I-NEXT: addiw a2, a2, -1
250 ; RV64I-NEXT: addiw a2, a2, -1
328 ; RV64I-NEXT: addiw a1, a1, -1
333 ; RV64I-NEXT: addiw a1, a1, -1
435 ; RV64I-NEXT: addiw a1, a1, -1
439 ; RV64I-NEXT: addiw a1, a1, -1
Drv64m-w-insts-legalization.ll14 ; CHECK-NEXT: addiw a0, a0, 1

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