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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td35 def : AT<"S1E1R", 0b01, 0b000, 0b0111, 0b1000, 0b000>;
36 def : AT<"S1E2R", 0b01, 0b100, 0b0111, 0b1000, 0b000>;
37 def : AT<"S1E3R", 0b01, 0b110, 0b0111, 0b1000, 0b000>;
38 def : AT<"S1E1W", 0b01, 0b000, 0b0111, 0b1000, 0b001>;
41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
42 def : AT<"S1E0W", 0b01, 0b000, 0b0111, 0b1000, 0b011>;
47 def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>;
48 def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>;
95 def : DC<"IVAC", 0b01, 0b000, 0b0111, 0b0110, 0b001>;
96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td53 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;
54 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
55 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;
56 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;
59 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
60 def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;
67 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
68 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
115 def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;
116 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
[all …]
DAArch64SVEInstrInfo.td87 defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add", add>;
99 defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", int_aarch64_sve_add>;
103 defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", int_aarch64_sve_orr>;
108 defm ADD_ZI : sve_int_arith_imm0<0b000, "add", add>;
122 defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv", int_aarch64_sve_saddv>;
124 defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv", AArch64smaxv_pred>;
128 defm ORV_VPZ : sve_int_reduce_2<0b000, "orv", AArch64orv_pred>;
142 defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul", int_aarch64_sve_mul>;
157 defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb", int_aarch64_sve_sxtb>;
166 defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls", int_aarch64_sve_cls>;
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td58 def : AT<"S1E1R", 0b000, 0b0111, 0b1000, 0b000>;
59 def : AT<"S1E2R", 0b100, 0b0111, 0b1000, 0b000>;
60 def : AT<"S1E3R", 0b110, 0b0111, 0b1000, 0b000>;
61 def : AT<"S1E1W", 0b000, 0b0111, 0b1000, 0b001>;
64 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
65 def : AT<"S1E0W", 0b000, 0b0111, 0b1000, 0b011>;
72 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
73 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
120 def : DC<"IVAC", 0b000, 0b0111, 0b0110, 0b001>;
121 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
[all …]
DAArch64SVEInstrInfo.td279 defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add", add, null_frag>;
291 …defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", "ADD_ZPZZ", int_aarch64_sve_add, Destructi…
304 defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", int_aarch64_sve_orr>;
309 defm ADD_ZI : sve_int_arith_imm0<0b000, "add", add, null_frag>;
323 defm SADDV_VPZ : sve_int_reduce_0_saddv<0b000, "saddv", AArch64saddv_p>;
325 defm SMAXV_VPZ : sve_int_reduce_1<0b000, "smaxv", AArch64smaxv_p>;
329 defm ORV_VPZ : sve_int_reduce_2<0b000, "orv", AArch64orv_p>;
343 …defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul", "MUL_ZPZZ", int_aarch64_sve_mul, Des…
363 defm SXTB_ZPmZ : sve_int_un_pred_arit_0_h<0b000, "sxtb", AArch64sxt_mt>;
372 defm CLS_ZPmZ : sve_int_un_pred_arit_1< 0b000, "cls", int_aarch64_sve_cls>;
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/external/llvm/lib/Target/Hexagon/
DHexagonSystemInst.td62 "dccleana($Rs)", [], 0b000, 0b000, 0b0>;
64 "dcinva($Rs)", [], 0b000, 0b000, 0b1>;
66 "dccleaninva($Rs)", [], 0b000, 0b001, 0b0>;
72 "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>;
DHexagonInstrInfoV5.td60 def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
65 def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>,
173 def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>;
174 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
177 def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>;
189 def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>;
211 def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>;
272 def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>;
277 def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>;
607 def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000,
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DHexagonInstrInfo.td188 def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
203 def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
221 defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;
222 defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>;
243 def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>;
246 def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>;
247 def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>;
248 def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>;
249 def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>;
802 defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel;
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DHexagonInstrEnc.td486 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
505 let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} };
559 let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} };
573 let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} };
669 let Inst{13-0} = { src2{0}, 0b000, opc{3}, 0, opc{2-0}, dst{4-0} };
712 let Inst{13-0} = { src3{0}, src1{1-0}, 0b000, opc{2-0}, src4{4-0} };
765 let Inst{13-0} = { opc{2}, 0b000, src1{1-0}, opc{1-0}, 1, dst{4-0} };
860 let Inst{13-0} = { 0b0000, src1{1-0}, 0b000, opc{2-0}, dst{1-0} };
863 class V6_pred_and_enc : Enc_COPROC_VX_3op_q<0b000>;
908 let Inst{13-0} = { opc{2}, 0b000000, opc{1}, 0b000, opc{0}, dst{1-0} };
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td114 def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">;
117 def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">;
126 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">,
133 def FLE_D : FPCmpD_rr<0b000, "fle.d">;
152 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
157 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
176 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">,
193 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">,
DRISCVInstrInfo.td364 : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
384 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
390 def BEQ : BranchCC_rri<0b000, "beq">;
397 def LB : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
403 def SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
410 def ADDI : ALU_ri<0b000, "addi">;
426 def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
427 def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
438 def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
449 def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> {
[all …]
DRISCVInstrInfoM.td27 def MUL : ALU_rr<0b0000001, 0b000, "mul">,
46 def MULW : ALUW_rr<0b0000001, 0b000, "mulw">,
DRISCVInstrInfoC.td283 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
363 def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,
370 def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
379 def C_ADDI_NOP : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
476 def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
590 def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
597 def C_ADDI_HINT_X0 : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
606 def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
648 def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
658 def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td116 def FSGNJ_D : FPALUD_rr<0b0010001, 0b000, "fsgnj.d">,
122 def FMIN_D : FPALUD_rr<0b0010101, 0b000, "fmin.d">,
133 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR32, "fcvt.d.s">,
140 def FLE_D : FPCmpD_rr<0b000, "fle.d">;
159 def FCVT_D_W : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.w">,
164 def FCVT_D_WU : FPUnaryOp_r<0b1101001, 0b000, FPR64, GPR, "fcvt.d.wu">,
183 def FMV_X_D : FPUnaryOp_r<0b1110001, 0b000, GPR, FPR64, "fmv.x.d">,
200 def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x">,
DRISCVInstrInfoZfh.td117 def FSGNJ_H : FPALUH_rr<0b0010010, 0b000, "fsgnj.h">,
124 def FMIN_H : FPALUH_rr<0b0010110, 0b000, "fmin.h">,
159 def FCVT_S_H : FPUnaryOp_r<0b0100000, 0b000, FPR32, FPR16, "fcvt.s.h">,
164 def FMV_X_H : FPUnaryOp_r<0b1110010, 0b000, GPR, FPR16, "fmv.x.h">,
169 def FMV_H_X : FPUnaryOp_r<0b1111010, 0b000, FPR16, GPR, "fmv.h.x">,
176 def FLE_H : FPCmpH_rr<0b000, "fle.h">;
217 def FCVT_D_H : FPUnaryOp_r<0b0100001, 0b000, FPR64, FPR16, "fcvt.d.h">,
DRISCVInstrInfoM.td27 def MUL : ALU_rr<0b0000001, 0b000, "mul">,
46 def MULW : ALUW_rr<0b0000001, 0b000, "mulw">,
DRISCVInstrInfo.td414 : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
434 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
440 def BEQ : BranchCC_rri<0b000, "beq">;
447 def LB : Load_ri<0b000, "lb">, Sched<[WriteLDB, ReadMemBase]>;
453 def SB : Store_rri<0b000, "sb">, Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
460 def ADDI : ALU_ri<0b000, "addi">;
476 def ADD : ALU_rr<0b0000000, 0b000, "add">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
477 def SUB : ALU_rr<0b0100000, 0b000, "sub">, Sched<[WriteIALU, ReadIALU, ReadIALU]>;
488 def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
499 def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", "">, Sched<[]> {
[all …]
DRISCVInstrInfoC.td287 def C_ADDI4SPN : RVInst16CIW<0b000, 0b00, (outs GPRC:$rd),
367 def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,
374 def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
383 def C_ADDI_NOP : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
480 def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
595 def C_NOP_HINT : RVInst16CI<0b000, 0b01, (outs), (ins simm6nonzero:$imm),
602 def C_ADDI_HINT_X0 : RVInst16CI<0b000, 0b01, (outs GPRX0:$rd_wb),
611 def C_ADDI_HINT_IMM_ZERO : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
653 def C_SLLI_HINT : RVInst16CI<0b000, 0b10, (outs GPRX0:$rd_wb),
663 def C_SLLI64_HINT : RVInst16CI<0b000, 0b10, (outs GPR:$rd_wb), (ins GPR:$rd),
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td397 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
398 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
399 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
400 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
417 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
418 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
419 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
420 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
422 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
423 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td411 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
412 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
413 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
414 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
431 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
432 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
433 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
434 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
436 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
437 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td411 class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
412 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
413 class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
414 class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
431 class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
432 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
433 class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
434 class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
436 class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
437 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
[all …]
/external/arm-trusted-firmware/fdts/
Dstm32mp15xxaa-pinctrl.dtsi64 gpioj: gpio@5000b000 {
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td48 let Inst{7-5} = 0b000;
100 let Inst{7-5} = 0b000;
176 let Inst{7-5} = 0b000;
256 let Inst{7-5} = 0b000;
298 let Inst{7-5} = 0b000;
330 let Inst{7-5} = 0b000;
364 let Inst{7-5} = 0b000;
376 let Inst{7-5} = 0b000;
388 let Inst{7-5} = 0b000;
400 let Inst{7-5} = 0b000;
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td48 let Inst{7-5} = 0b000;
100 let Inst{7-5} = 0b000;
176 let Inst{7-5} = 0b000;
256 let Inst{7-5} = 0b000;
298 let Inst{7-5} = 0b000;
330 let Inst{7-5} = 0b000;
364 let Inst{7-5} = 0b000;
376 let Inst{7-5} = 0b000;
388 let Inst{7-5} = 0b000;
400 let Inst{7-5} = 0b000;
[all …]
/external/exoplayer/tree/library/core/src/main/java/com/google/android/exoplayer2/
DRendererCapabilities.java89 int FORMAT_UNSUPPORTED_TYPE = 0b000;

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