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/external/llvm-project/clang/test/Modules/Inputs/PR27513/
Dmodule.modulemap6 module "b1111.h" { header "b1111.h" export *}
/external/clang/test/Modules/Inputs/PR27513/
Dmodule.modulemap6 module "b1111.h" { header "b1111.h" export *}
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td876 let Inst{19-16} = 0b1111; // Rn
888 let Inst{15-12} = 0b1111;
934 let Inst{11-8} = 0b1111; // Rd
946 let Inst{11-8} = 0b1111; // Rd
960 let Inst{11-8} = 0b1111; // Rd
1048 let Inst{19-16} = 0b1111; // Rn
1131 let Inst{19-16} = 0b1111; // Rn
1132 let Inst{15-12} = 0b1111;
1149 let Inst{19-16} = 0b1111; // Rn
1150 let Inst{15-12} = 0b1111;
[all …]
DARMInstrInfo.td1474 let Unpredictable{15-12} = 0b1111;
1491 let Unpredictable{15-12} = 0b1111;
1508 let Unpredictable{15-12} = 0b1111;
1527 let Unpredictable{15-12} = 0b1111;
1544 let Inst{19-16} = 0b1111;
1555 let Inst{19-16} = 0b1111;
1930 let Inst{11-8} = 0b1111;
1931 let Unpredictable{11-8} = 0b1111;
1968 let Inst{31-28} = 0b1111;
2005 let Inst{15-12} = 0b1111;
[all …]
DARMInstrNEON.td670 let Rm = 0b1111;
678 let Rm = 0b1111;
743 let Rm = 0b1111;
784 let Rm = 0b1111;
826 let Rm = 0b1111;
909 let Rm = 0b1111;
968 let Rm = 0b1111;
1060 let Rm = 0b1111;
1072 let Rm = 0b1111;
1139 let Rm = 0b1111;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td633 def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;
640 def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;
654 def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;
752 def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>;
768 def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>;
784 def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>;
800 def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>;
949 def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;
974 def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;
975 def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;
[all …]
DAArch64SVEInstrInfo.td327 defm NANDS_PPzPP : sve_int_pred_log<0b1111, "nands", null_frag>;
357 defm LD1D_IMM : sve_mem_cld_si<0b1111, "ld1d", Z_d, ZPR64>;
403 defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
421 defm LDNF1D_IMM : sve_mem_cldnf_si<0b1111, "ldnf1d", Z_d, ZPR64>;
439 defm LDFF1D : sve_mem_cldff_ss<0b1111, "ldff1d", Z_d, ZPR64, GPR64shifted64>;
519 …defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8, null_frag, …
536 …defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d", null_frag, nxv2i64>;
549 …defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", null_frag, ZP…
566 …defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", null_frag, nul…
579 …defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", null_frag, null_frag, …
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td638 def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;
645 def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;
659 def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;
757 def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>;
773 def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>;
789 def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>;
805 def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>;
954 def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;
979 def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;
980 def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;
[all …]
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp142 b1111 = 0xF, enumerator
147 { false, false, false, b0001, b1000, b1111, false, NONE },
150 { true, false, false, b1111, b1111, b0000, false, NONE },
153 { false, true, true, b1010, b1010, b1111, false, NONE },
156 { true, true, true, b0010, b1000, b1111, true, FILL },
157 { true, true, true, b1001, b1001, b1111, true, FILL },
159 { true, true, true, b0010, b1000, b1111, true, COPY },
160 { true, true, true, b1001, b1001, b1111, true, COPY },
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td381 def : ROSysReg<"TRCIDR7", 0b10, 0b001, 0b0000, 0b1111, 0b111>;
388 def : ROSysReg<"TRCDEVARCH", 0b10, 0b001, 0b0111, 0b1111, 0b110>;
402 def : ROSysReg<"TRCCIDR3", 0b10, 0b001, 0b0111, 0b1111, 0b111>;
478 def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>;
494 def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>;
510 def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>;
526 def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>;
675 def : RWSysReg<"PMCCFILTR_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b111>;
700 def : RWSysReg<"PMEVTYPER24_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b000>;
701 def : RWSysReg<"PMEVTYPER25_EL0", 0b11, 0b011, 0b1110, 0b1111, 0b001>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td1068 let Inst{19-16} = 0b1111; // Rn
1081 let Inst{15-12} = 0b1111;
1127 let Inst{11-8} = 0b1111; // Rd
1139 let Inst{11-8} = 0b1111; // Rd
1153 let Inst{11-8} = 0b1111; // Rd
1245 let Inst{19-16} = 0b1111; // Rn
1331 let Inst{19-16} = 0b1111; // Rn
1332 let Inst{15-12} = 0b1111;
1366 let Inst{15-12} = 0b1111;
1402 let Inst{19-16} = 0b1111; // Rn
[all …]
DARMInstrInfo.td1616 let Unpredictable{15-12} = 0b1111;
1633 let Unpredictable{15-12} = 0b1111;
1650 let Unpredictable{15-12} = 0b1111;
1669 let Unpredictable{15-12} = 0b1111;
1686 let Inst{19-16} = 0b1111;
1697 let Inst{19-16} = 0b1111;
2075 let Inst{11-8} = 0b1111;
2076 let Unpredictable{11-8} = 0b1111;
2113 let Inst{31-28} = 0b1111;
2150 let Inst{15-12} = 0b1111;
[all …]
DARMInstrNEON.td627 let Rm = 0b1111;
635 let Rm = 0b1111;
700 let Rm = 0b1111;
753 let Rm = 0b1111;
807 let Rm = 0b1111;
890 let Rm = 0b1111;
950 let Rm = 0b1111;
1042 let Rm = 0b1111;
1054 let Rm = 0b1111;
1146 let Rm = 0b1111;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb2.td1069 let Inst{19-16} = 0b1111; // Rn
1082 let Inst{15-12} = 0b1111;
1128 let Inst{11-8} = 0b1111; // Rd
1140 let Inst{11-8} = 0b1111; // Rd
1154 let Inst{11-8} = 0b1111; // Rd
1246 let Inst{19-16} = 0b1111; // Rn
1332 let Inst{19-16} = 0b1111; // Rn
1333 let Inst{15-12} = 0b1111;
1367 let Inst{15-12} = 0b1111;
1403 let Inst{19-16} = 0b1111; // Rn
[all …]
DARMInstrInfo.td1731 let Unpredictable{15-12} = 0b1111;
1748 let Unpredictable{15-12} = 0b1111;
1765 let Unpredictable{15-12} = 0b1111;
1784 let Unpredictable{15-12} = 0b1111;
1801 let Inst{19-16} = 0b1111;
1812 let Inst{19-16} = 0b1111;
2190 let Inst{11-8} = 0b1111;
2191 let Unpredictable{11-8} = 0b1111;
2228 let Inst{31-28} = 0b1111;
2265 let Inst{15-12} = 0b1111;
[all …]
DARMInstrNEON.td603 let Rm = 0b1111;
611 let Rm = 0b1111;
676 let Rm = 0b1111;
729 let Rm = 0b1111;
783 let Rm = 0b1111;
866 let Rm = 0b1111;
926 let Rm = 0b1111;
1018 let Rm = 0b1111;
1030 let Rm = 0b1111;
1128 let Rm = 0b1111;
[all …]
/external/mp4parser/isoparser/src/main/java/com/googlecode/mp4parser/boxes/mp4/objectdescriptors/
DObjectDescriptor.java_bak30 const bit(5) reserved=0b1111.1;
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h117 TEEE = 0b1111,
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td457 class V6_vS32b_nt_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1111>;
474 class V6_vS32b_nt_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1111>;
644 class V6_vS32b_nt_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1111>;
661 class V6_vS32b_nt_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1111>;
739 class V6_vS32b_nt_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b1111>;
833 class V6_vlutvwh_oracc_enc : Enc_COPROC_VX_4op_r<0b1111>;
/external/llvm-project/llvm/lib/Target/RISCV/Utils/
DRISCVBaseInfo.h51 ConstraintMask = 0b1111
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dapint-add.ll46 ;; (x & 0b1111..0) + 1 -> x | 1
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt391 # VMOV cmode=0b1111 op=1 is UNDEFINED
396 # VMOV cmode=0b1111 op=1 is UNDEFINED
/external/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td433 let Opcode = 0b1111;
461 let Opcode = 0b1111;
512 let Opcode = 0b1111;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td432 let Opcode = 0b1111;
460 let Opcode = 0b1111;
511 let Opcode = 0b1111;
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td432 let Opcode = 0b1111;
460 let Opcode = 0b1111;
511 let Opcode = 0b1111;

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