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Searched refs:brw_emit_pipe_control_flush (Results 1 – 19 of 19) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_pipe_control.c37 brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags) in brw_emit_pipe_control_flush() function
105 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in brw_emit_depth_stall_flushes()
106 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH); in brw_emit_depth_stall_flushes()
107 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in brw_emit_depth_stall_flushes()
240 brw_emit_pipe_control_flush(brw, in brw_emit_post_sync_nonzero_flush()
346 brw_emit_pipe_control_flush(brw, flags); in brw_emit_end_of_pipe_sync()
371 brw_emit_pipe_control_flush(brw, flags); in brw_emit_mi_flush()
Dgen8_depth_state.c150 brw_emit_pipe_control_flush(brw, in gen8_write_pma_stall_bits()
164 brw_emit_pipe_control_flush(brw, in gen8_write_pma_stall_bits()
Dbrw_conditional_render.c65 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_overflow_query()
87 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in set_predicate_for_occlusion_query()
Dgen7_l3_state.c87 brw_emit_pipe_control_flush(brw, in setup_l3_config()
105 brw_emit_pipe_control_flush(brw, in setup_l3_config()
114 brw_emit_pipe_control_flush(brw, in setup_l3_config()
Dbrw_pipe_control.h83 void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
Dbrw_misc_state.c531 brw_emit_pipe_control_flush(brw, in brw_emit_select_pipeline()
537 brw_emit_pipe_control_flush(brw, in brw_emit_select_pipeline()
683 brw_emit_pipe_control_flush(brw, in brw_emit_hashing_mode()
895 brw_emit_pipe_control_flush(brw, in brw_upload_state_base_address()
Dbrw_blorp.c524 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
534 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL | in brw_blorp_copy_miptrees()
1615 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1641 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1645 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in intel_hiz_exec()
1671 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1674 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
1691 brw_emit_pipe_control_flush(brw, in intel_hiz_exec()
Dintel_tex.c313 brw_emit_pipe_control_flush(brw, in intel_texture_barrier()
318 brw_emit_pipe_control_flush(brw, in intel_texture_barrier()
DgenX_blorp_exec.c229 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL); in blorp_vf_invalidate_for_vb_48b_transitions()
300 brw_emit_pipe_control_flush(brw, in genX()
Dbrw_queryobj.c83 brw_emit_pipe_control_flush(brw, in brw_write_timestamp()
114 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL); in brw_write_depth_count()
Dbrw_program.c381 brw_emit_pipe_control_flush(brw, bits); in brw_memory_barrier()
392 brw_emit_pipe_control_flush(brw, in brw_framebuffer_fetch_barrier()
395 brw_emit_pipe_control_flush(brw, in brw_framebuffer_fetch_barrier()
398 brw_emit_pipe_control_flush(brw, in brw_framebuffer_fetch_barrier()
Dbrw_draw.c442 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); in gen9_apply_astc5x5_wa_flush()
443 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); in gen9_apply_astc5x5_wa_flush()
1196 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); in brw_draw_prims()
Dintel_fbo.c1021 brw_emit_pipe_control_flush(brw, in flush_depth_and_render_caches()
1026 brw_emit_pipe_control_flush(brw, in flush_depth_and_render_caches()
Dhsw_queryobj.c292 brw_emit_pipe_control_flush(brw, in hsw_result_to_gpr0()
DgenX_state_upload.c438 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL); in vf_invalidate_for_vb_48bit_transitions()
450 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_VF_CACHE_INVALIDATE); in vf_invalidate_for_ib_48bit_transition()
2227 brw_emit_pipe_control_flush(brw,
4298 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
Dintel_batchbuffer.c641 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH | in brw_finish_batch()
Dintel_mipmap_tree.c3268 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL); in intel_miptree_set_clear_color()
3274 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE); in intel_miptree_set_clear_color()
Dbrw_wm_surface_state.c1042 brw_emit_pipe_control_flush(brw, in update_renderbuffer_surfaces()
/external/mesa3d/docs/relnotes/
D12.0.2.rst163 brw_emit_pipe_control_flush.
166 brw_emit_pipe_control_flush.