| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| D | ir3_const.h | 71 assert(regid + sizedwords <= v->constlen * 4); in emit_const_asserts()
134 if (16 * v->constlen <= state->range[i].offset) in ir3_emit_user_consts()
140 size = MIN2(size, (16 * v->constlen) - state->range[i].offset); in ir3_emit_user_consts()
173 if (v->constlen > offset) { in ir3_emit_ubos()
204 assert(offset * 4 + params <= v->constlen * 4); in ir3_emit_ubos()
216 if (v->constlen > offset) { in ir3_emit_ssbo_sizes()
236 if (v->constlen > offset) { in ir3_emit_image_dims()
277 uint32_t size = MIN2(ARRAY_SIZE(dims), v->constlen * 4 - offset * 4); in ir3_emit_image_dims()
294 size = MIN2(size + base, v->constlen) - base; in ir3_emit_immediates()
316 size = MIN2(size + base, v->constlen) - base; in ir3_emit_link_map()
[all …]
|
| D | ir3_gallium.c | 67 v->constlen, in dump_shader_info()
225 if (v->constlen > compiler->max_const_safe) { in ir3_shader_create()
236 if (v->constlen > compiler->max_const_safe) { in ir3_shader_create()
|
| /external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| D | fd4_program.c | 86 uint8_t constlen; member
115 assert(s[i].v->constlen % 4 == 0); in setup_stages()
116 s[i].constlen = s[i].v->constlen / 4; in setup_stages()
124 s[i].constlen = 0; in setup_stages()
151 s[VS].constlen = 66; in setup_stages()
152 s[FS].constlen = 128 - s[VS].constlen; in setup_stages()
156 s[FS].constoff = s[VS].constlen; in setup_stages()
247 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) | in fd4_program_emit()
251 OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) | in fd4_program_emit()
255 OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) | in fd4_program_emit()
[all …]
|
| D | fd4_emit.c | 134 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
|
| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| D | fd3_program.c | 159 constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0; in fd3_program_emit()
214 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) | in fd3_program_emit()
217 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) | in fd3_program_emit()
239 OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) | in fd3_program_emit()
241 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen - 1, 0))); in fd3_program_emit()
310 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) | in fd3_program_emit()
312 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen - 1, 0)) | in fd3_program_emit()
317 MAX2(128, vp->constlen)) | in fd3_program_emit()
|
| D | fd3_emit.c | 143 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
|
| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| D | fd5_compute.c | 125 assert(v->constlen % 4 == 0); in cs_program_emit()
126 unsigned constlen = v->constlen / 4; in cs_program_emit() local
128 OUT_RING(ring, constlen); /* HLSQ_CS_CONSTLEN */ in cs_program_emit()
|
| D | fd5_program.c | 206 uint8_t constlen; member
235 assert(s[i].v->constlen % 4 == 0); in setup_stages()
236 s[i].constlen = s[i].v->constlen / 4; in setup_stages()
244 s[i].constlen = 0; in setup_stages()
275 constoff += s[i].constlen; in setup_stages()
384 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */ in fd5_program_emit()
388 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */ in fd5_program_emit()
392 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */ in fd5_program_emit()
396 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */ in fd5_program_emit()
400 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */ in fd5_program_emit()
|
| D | fd5_emit.c | 141 assert(dst_offset + num <= v->constlen * 4); in emit_const_ptrs()
|
| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_shader.c | 138 v->constlen = MAX2(v->constlen, v->info.max_const + 1); in ir3_shader_assemble()
145 v->constlen = align(v->constlen, 4); in ir3_shader_assemble()
442 constlens[i] = variants[i]->constlen; in ir3_trim_constlen()
625 so->constlen); in ir3_shader_disasm()
|
| D | ir3_shader.h | 544 unsigned constlen; member
|
| D | ir3_compiler_nir.c | 776 ctx->so->constlen = MAX2(ctx->so->constlen, in emit_intrinsic_load_ubo()
1519 ctx->so->constlen = MAX2(ctx->so->constlen, in emit_intrinsic()
|
| D | disasm-a3xx.c | 371 if (max > ctx->stats->constlen) in print_src()
372 ctx->stats->constlen = max; in print_src()
|
| /external/mesa3d/src/freedreno/computerator/ |
| D | a6xx.c | 133 unsigned constlen = align(v->constlen, 4); in cs_program_emit() local
135 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(constlen) | in cs_program_emit()
236 size = MIN2(size + base, v->constlen) - base; in cs_const_emit()
|
| /external/mesa3d/src/freedreno/common/ |
| D | disasm.h | 46 int constlen; member
|
| /external/mesa3d/src/gallium/drivers/freedreno/a6xx/ |
| D | fd6_program.c | 249 debug_assert(state->vs->constlen >= state->bs->constlen); in setup_config_stateobj()
252 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) | in setup_config_stateobj()
256 A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen))); in setup_config_stateobj()
259 A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen))); in setup_config_stateobj()
262 A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen))); in setup_config_stateobj()
264 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) | in setup_config_stateobj()
|
| D | fd6_compute.c | 94 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_CONSTLEN(v->constlen) | in cs_program_emit()
|
| D | fd6_const.c | 155 int size = MIN2(1 + regid, v->constlen) - regid; in emit_stage_tess_consts()
|
| /external/mesa3d/src/freedreno/decode/ |
| D | pgmdump2.c | 381 stats.constlen, stats.ss, stats.sy, in decode_shader_descriptor_block()
|
| /external/mesa3d/src/freedreno/vulkan/ |
| D | tu_pipeline.c | 425 tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) | in tu6_emit_xs_config()
454 size = MIN2(size + base, xs->constlen) - base; in tu6_emit_xs_config()
739 size = (MIN2(size + base, consumer->constlen) - base) * 4; in tu6_emit_link_map()
2248 link->constlen = v->constlen; in tu_pipeline_set_linkage()
|
| D | tu_private.h | 1062 uint32_t constlen; member
|
| D | tu_cmd_buffer.c | 3040 size = MIN2(size, (16 * link->constlen) - state->range[i].offset); in tu6_emit_user_consts()
3453 if (const_state->offsets.driver_param >= link->constlen) in vs_params_offset()
3760 if (link->constlen <= offset) in tu_emit_compute_driver_params()
3774 (link->constlen - offset) * 4); in tu_emit_compute_driver_params()
|
| D | tu_clear_blit.c | 360 .constlen = 4, in r3d_common()
389 .constlen = align(num_rts, 4), in r3d_common()
|
| /external/mesa3d/docs/relnotes/ |
| D | 10.3.3.rst | 123 - freedreno/ir3: fix constlen with relative addressing
|
| D | 20.2.0.rst | 1164 - ir3, freedreno: Round up constlen earlier
1166 - ir3: Support variants with different constlen's
1168 - tu: Share constlen between different stages properly
1170 - freedreno: Share constlen between different stages properly
1702 - freedreno: Fix attempts to push UBO contents past the constlen on pre-a6xx.
|