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Searched refs:constrainOperandRegClass (Results 1 – 25 of 32) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h57 unsigned constrainOperandRegClass(const MachineFunction &MF,
75 unsigned constrainOperandRegClass(const MachineFunction &MF,
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h59 Register constrainOperandRegClass(const MachineFunction &MF,
77 Register constrainOperandRegClass(const MachineFunction &MF,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp40 unsigned llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
70 unsigned llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
107 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
144 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
DInstructionSelector.cpp44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, in constrainOperandRegToRegClass()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp286 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
309 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
310 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
337 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
364 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rri()
365 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rri()
532 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
605 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
681 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1068 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMFastISel.cpp309 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
332 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
333 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
360 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
524 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
601 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
677 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1066 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1140 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1277 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMFastISel.cpp308 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
331 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
332 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
359 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
515 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
588 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0); in ARMMaterializeGV()
664 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
1053 SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1); in ARMEmitStore()
1127 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1264 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
[all …]
DARMCallLowering.cpp531 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( in lowerCall()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DInstructionSelector.cpp44 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, in constrainOperandRegToRegClass()
DUtils.cpp46 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
84 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
121 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass, in constrainOperandRegClass()
158 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), in constrainSelectedInstRegOperands()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1789 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
1821 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1844 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1868 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1869 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1870 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
1917 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
1961 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp2088 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, in constrainOperandRegClass() function in FastISel
2120 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2142 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2143 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2167 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2168 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2169 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2193 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2216 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2260 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp2023 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op, in constrainOperandRegClass() function in FastISel
2055 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
2077 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2078 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
2102 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
2103 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
2104 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2151 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2195 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1139 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1141 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1342 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1343 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1387 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1429 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1430 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1474 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1475 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2100 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1141 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1143 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1344 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1345 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1431 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1432 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1476 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1477 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2102 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
[all …]
DAArch64CallLowering.cpp911 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerTailCall()
997 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp1062 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1064 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1261 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1262 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1306 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1346 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1347 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1390 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2060 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
[all …]
/external/llvm/include/llvm/CodeGen/
DFastISel.h476 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
/external/llvm-project/llvm/include/llvm/CodeGen/
DFastISel.h475 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DFastISel.h476 unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp935 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerTailCall()
1020 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
/external/llvm-project/llvm/lib/Target/X86/
DX86FastISel.cpp229 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
646 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3976 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
3999 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
4000 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
4001 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
4002 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
DX86CallLowering.cpp448 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FastISel.cpp230 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
647 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3961 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
3984 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
3985 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
3986 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
3987 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
DX86CallLowering.cpp451 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()

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