Home
last modified time | relevance | path

Searched refs:dlc (Results 1 – 25 of 58) sorted by relevance

123

/external/llvm-project/llvm/test/MC/AMDGPU/
Dflat-scratch-instructions.s13 scratch_load_ubyte v1, v2, off dlc
23 scratch_load_sbyte v1, v2, off dlc
33 scratch_load_ushort v1, v2, off dlc
43 scratch_load_sshort v1, v2, off dlc
53 scratch_load_dword v1, v2, off dlc
63 scratch_load_dwordx2 v[1:2], v3, off dlc
73 scratch_load_dwordx3 v[1:3], v4, off dlc
83 scratch_load_dwordx4 v[1:4], v5, off dlc
143 scratch_store_byte v1, v2, off dlc
153 scratch_store_short v1, v2, off dlc
[all …]
Dflat-global.s13 global_load_ubyte v1, v[3:4], off dlc
23 global_load_sbyte v1, v[3:4], off dlc
33 global_load_ushort v1, v[3:4], off dlc
43 global_load_sshort v1, v[3:4], off dlc
53 global_load_dword v1, v[3:4], off dlc
63 global_load_dwordx2 v[1:2], v[3:4], off dlc
73 global_load_dwordx3 v[1:3], v[3:4], off dlc
83 global_load_dwordx4 v[1:4], v[3:4], off dlc
124 global_store_byte v[3:4], v1, off dlc
134 global_store_short v[3:4], v1, off dlc
[all …]
Dmubuf-gfx10.s6 buffer_load_sbyte v5, off, s[8:11], s3 glc slc lds dlc
9 buffer_load_sbyte v5, off, s[8:11], s3 glc slc dlc
Dgfx1030_new.s9 global_load_dword_addtid v1, s[2:3] offset:16 glc slc dlc
12 global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc
Dflat-gfx10.s22 flat_load_dword v1, v[3:4] offset:4 glc slc dlc
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsmrd-gfx10.ll4 ; GCN: s_buffer_load_dword s0, s[0:3], 0x0 dlc ; encoding: [0x00,0x40,0x20,0xf4,0x00,0x00,0x00,0xfa]
12 ; GCN: s_buffer_load_dword s0, s[0:3], s4 dlc ; encoding: [0x00,0x40,0x20,0xf4,0x00,0x00,0x00,0x08]
20 ; GCN: s_buffer_load_dword s0, s[0:3], 0x0 glc dlc ; encoding: [0x00,0x40,0x21,0xf4,0x00,0x00,0x00,…
28 ; GCN: s_buffer_load_dword s0, s[0:3], s4 glc dlc ; encoding: [0x00,0x40,0x21,0xf4,0x00,0x00,0x00,0…
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSMInstructions.td114 (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
115 " $sdst, $sbase, $offset$glc$dlc", []> {
125 (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
126 " $sdst, $sbase, $offset$glc$dlc", []> {
138 (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
139 " $sdata, $sbase, $offset$glc$dlc", []> {
147 (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
148 " $sdata, $sbase, $offset$glc$dlc", []> {
231 (ins dataClass:$sdata, baseClass:$sbase, smrd_offset_20:$offset, DLC:$dlc),
232 (ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset, DLC:$dlc)),
[all …]
DMIMGInstructions.td240 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
243 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
253 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
256 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
333 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
336 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
347 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
350 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
438 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
440 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe";
[all …]
DBUFInstructions.td101 bits<1> dlc_value = 0; // the value for dlc if no such operand
125 bits<1> dlc;
144 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
146 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
151 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
154 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
206 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc$swz",
222 i1:$glc, i1:$slc, i1:$tfe, i1:$dlc, i1:$swz)))]>,
228 i8:$format, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc, i1:$swz)))]>,
254 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc$swz",
[all …]
DFLATInstructions.td93 bits<1> dlc;
145 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
147 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
166 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
167 …" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
200 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
201 (ins VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
202 … "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc$dlc"> {
216 …ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
217 (ins vdataClass:$vdata, VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
[all …]
DSIFixupVectorISel.cpp200 MachineOperand *DLC = TII->getNamedOperand(MI, AMDGPU::OpName::dlc); in fixupGlobalSaddr()
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dflat_gfx10.txt7 # CHECK: scratch_load_dword v1, v255, off offset:-1 glc dlc ; encoding: [0xff,0x5f,0x31,0xdc,0xff,0…
13 # CHECK: scratch_load_dword v0, v1, off offset:-2048 glc slc dlc ; encoding: [0x00,0x58,0x33,0xdc,0…
16 # CHECK: scratch_load_dword v255, off, s105 offset:2047 dlc ; encoding: [0xff,0x57,0x30,0xdc,0x00,0…
22 # CHECK: scratch_load_dword v5, v0, off dlc ; encoding: [0x00,0x50,0x30,0xdc,0x00,0x00,0x7d,0x05]
28 # CHECK: scratch_load_dword v5, v255, off slc dlc ; encoding: [0x00,0x50,0x32,0xdc,0xff,0x00,0x7d,0…
74 # CHECK: scratch_store_dword off, v2, s3 offset:-1 dlc ; encoding: [0xff,0x5f,0x70,0xdc,0x00,0x02,0…
Dgfx1030_dasm_new.txt9 # GFX10: global_load_dword_addtid v1, s[2:3] offset:16 glc slc dlc
12 # GFX10: global_store_dword_addtid v1, s[2:3] offset:16 glc slc dlc
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSMInstructions.td123 (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
124 " $sdst, $sbase, $offset$glc$dlc", []> {
134 (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
135 " $sdst, $sbase, $offset$glc$dlc", []> {
147 (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc, i1imm:$dlc),
148 " $sdata, $sbase, $offset$glc$dlc", []> {
156 (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc, i1imm:$dlc),
157 " $sdata, $sbase, $offset$glc$dlc", []> {
240 (ins dataClass:$sdata, baseClass:$sbase, smem_offset:$offset, DLC:$dlc),
241 (ins dataClass:$sdata, baseClass:$sbase, SReg_32:$offset, DLC:$dlc)),
[all …]
DMIMGInstructions.td256 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
259 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
269 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
272 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
349 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
352 let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
363 Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
366 let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe"
454 DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
456 let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$a16$tfe$lwe";
[all …]
DBUFInstructions.td101 bits<1> dlc_value = 0; // the value for dlc if no such operand
126 bits<1> dlc;
145 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
147 offset:$offset, FORMAT:$format, GLC:$glc, SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
152 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz),
155 SLC:$slc, TFE:$tfe, DLC:$dlc, SWZ:$swz)
207 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc$swz",
223 i1:$glc, i1:$slc, i1:$tfe, i1:$dlc, i1:$swz)))]>,
229 i8:$format, i1:$glc, i1:$slc, i1:$tfe, i1:$dlc, i1:$swz)))]>,
255 " $vdata, " # getMTBUFAsmOps<addrKindCopy>.ret # "$glc$slc$tfe$dlc$swz",
[all …]
DFLATInstructions.td97 bits<1> dlc;
152 !if(HasTiedOutput, (ins GLC:$glc, SLC:$slc, DLC:$dlc, regClass:$vdst_in),
153 (ins GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc))),
154 " $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
174 (ins flat_offset:$offset, GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc)),
175 …" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
198 !con((ins SReg_64:$saddr, flat_offset:$offset, GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc),
200 " $vdst, $saddr$offset$glc$slc$dlc"> {
228 (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
229 " $vdata, $saddr$offset$glc$slc$dlc"> {
[all …]
DSIInstrFormats.td311 bits<1> dlc;
317 let Inst{7} = dlc;
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX10.rst456 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
457 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
458 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
459 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
460 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
461 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
462 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
463 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
464 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
465 …t_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
[all …]
/external/mesa3d/src/amd/compiler/
Daco_opt_value_numbering.cpp234 aS->sync == bS->sync && aS->glc == bS->glc && aS->dlc == bS->dlc && in operator ()()
265 aM->dlc == bM->dlc && in operator ()()
279 aM->dlc == bM->dlc && in operator ()()
Daco_assembler.cpp199 assert(!smem->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
204 encoding |= smem->dlc ? 1 << 14 : 0; in emit_instruction()
372 assert(!mubuf->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
375 encoding |= (mubuf->dlc ? 1 : 0) << 15; in emit_instruction()
398 assert(!mtbuf->dlc || ctx.chip_class >= GFX10); in emit_instruction()
399 encoding |= (mtbuf->dlc ? 1 : 0) << 15; /* DLC bit replaces one bit of the OPCODE on GFX10 */ in emit_instruction()
440 assert(!mimg->dlc); /* Device-level coherent is not supported on GFX9 and lower */ in emit_instruction()
447 encoding |= mimg->dlc ? 1 << 7 : 0; in emit_instruction()
497 encoding |= flat->dlc ? 1 << 12 : 0; in emit_instruction()
499 assert(!flat->dlc); in emit_instruction()
Daco_print_ir.cpp341 if (smem->dlc) in print_instr_format_specific()
376 if (mubuf->dlc) in print_instr_format_specific()
430 if (mimg->dlc) in print_instr_format_specific()
507 if (flat->dlc) in print_instr_format_specific()
559 if (mtbuf->dlc) in print_instr_format_specific()
Daco_ir.h1014 bool dlc : 1; /* NAVI: device level coherent */ member
1168 bool dlc : 1; /* NAVI: device level coherent */ member
1194 bool dlc : 1; /* NAVI: device level coherent */ member
1217 bool dlc : 1; /* NAVI: device level coherent */ member
1242 bool dlc : 1; /* NAVI: device level coherent */ member
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td699 …lvm_i32_ty]), // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc)
873 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc)
904 // bit 2 = dlc on gfx10+),
919 // bit 2 = dlc on gfx10+),
934 // bit 2 = dlc on gfx10+),
950 // bit 2 = dlc on gfx10+),
1067 // bit 2 = dlc on gfx10+),
1081 // bit 2 = dlc on gfx10+),
1095 // bit 2 = dlc on gfx10+),
1110 // bit 2 = dlc on gfx10+),
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td726 …lvm_i32_ty]), // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc)
910 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc)
942 // bit 2 = dlc on gfx10+),
957 // bit 2 = dlc on gfx10+),
972 // bit 2 = dlc on gfx10+),
988 // bit 2 = dlc on gfx10+),
1114 // bit 2 = dlc on gfx10+),
1129 // bit 2 = dlc on gfx10+),
1144 // bit 2 = dlc on gfx10+),
1160 // bit 2 = dlc on gfx10+),

123