| /external/mesa3d/src/freedreno/decode/ |
| D | cffdec.c | 196 dump_hex(uint32_t *dwords, uint32_t sizedwords, int level) in dump_hex() argument
212 if (dwords[i+j]) in dump_hex()
223 uint64_t addr = gpuaddr(&dwords[i]); in dump_hex()
241 printf(" %08x", dwords[i+j]); in dump_hex()
249 dump_float(float *dwords, uint32_t sizedwords, int level) in dump_float() argument
255 printf("%016"PRIx64":%s", gpuaddr(dwords), levels[level]); in dump_float()
257 printf("%08x:%s", (uint32_t)gpuaddr(dwords), levels[level]); in dump_float()
262 printf("%8f", *(dwords++)); in dump_float()
882 dump_registers(uint32_t regbase, uint32_t *dwords, uint32_t sizedwords, int level) in dump_registers() argument
893 reg_set(regbase, *dwords); in dump_registers()
[all …]
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| /external/mesa3d/src/freedreno/.gitlab-ci/reference/ |
| D | dEQP-GLES2.functional.texture.specification.basic_teximage2d.rgba16f_2d.log | 5 cmdstream: 124 dwords
9 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
12 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
15 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
28 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
30 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
33 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
36 t3 opcode: CP_SET_CONSTANT (2d) (4 dwords)
40 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
43 t3 opcode: CP_SET_CONSTANT (2d) (3 dwords)
[all …]
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| D | es2gears-a320.log | 5 cmdstream: 488 dwords
6 t3 opcode: CP_INVALIDATE_STATE (3b) (2 dwords)
124 t3 opcode: CP_EVENT_WRITE (46) (2 dwords)
128 t3 opcode: CP_DRAW_INDX (22) (4 dwords)
137 t3 opcode: CP_NOP (10) (5 dwords)
139 t3 opcode: CP_WAIT_FOR_IDLE (26) (2 dwords)
194 t3 opcode: (null) (4c) (4 dwords)
224 t3 opcode: CP_REG_RMW (21) (4 dwords)
241 t3 opcode: CP_INDIRECT_BUFFER_PFD (37) (3 dwords)
263 t3 opcode: CP_REG_RMW (21) (4 dwords)
[all …]
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| D | dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log | 5 cmdstream: 265 dwords
6 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
13 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
192 t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords)
229 t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
236 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
240 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
275 t7 opcode: CP_BLIT (2c) (2 dwords)
371 t7 opcode: CP_EVENT_WRITE (46) (2 dwords)
375 t7 opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
[all …]
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| /external/igt-gpu-tools/lib/ |
| D | debug.h | 79 uint32_t *dwords = (uint32_t *)reg; in print_reg() local
81 dwords[7], dwords[6], dwords[5], dwords[4], in print_reg()
82 dwords[3], dwords[2], dwords[1], dwords[0]); in print_reg()
87 uint32_t *dwords = (uint32_t *)reg; in print_creg() local
88 printf("%08x %08x %08x", dwords[2], dwords[1], dwords[0]); in print_creg()
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | vec-conv-01.ll | 10 %dwords = fptosi <2 x double> %doubles to <2 x i64>
11 ret <2 x i64> %dwords
19 %dwords = fptoui <2 x double> %doubles to <2 x i64>
20 ret <2 x i64> %dwords
24 define <2 x double> @f3(<2 x i64> %dwords) {
28 %doubles = sitofp <2 x i64> %dwords to <2 x double>
33 define <2 x double> @f4(<2 x i64> %dwords) {
37 %doubles = uitofp <2 x i64> %dwords to <2 x double>
72 %dwords = fptosi <2 x float> %floats to <2 x i64>
73 ret <2 x i64> %dwords
[all …]
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| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | vec-conv-01.ll | 10 %dwords = fptosi <2 x double> %doubles to <2 x i64>
11 ret <2 x i64> %dwords
19 %dwords = fptoui <2 x double> %doubles to <2 x i64>
20 ret <2 x i64> %dwords
24 define <2 x double> @f3(<2 x i64> %dwords) {
28 %doubles = sitofp <2 x i64> %dwords to <2 x double>
33 define <2 x double> @f4(<2 x i64> %dwords) {
37 %doubles = uitofp <2 x i64> %dwords to <2 x double>
72 %dwords = fptosi <2 x float> %floats to <2 x i64>
73 ret <2 x i64> %dwords
[all …]
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| D | vec-conv-03.ll | 10 %dwords = fptosi <4 x float> %floats to <4 x i32>
11 ret <4 x i32> %dwords
19 %dwords = fptoui <4 x float> %floats to <4 x i32>
20 ret <4 x i32> %dwords
24 define <4 x float> @f3(<4 x i32> %dwords) {
28 %floats = sitofp <4 x i32> %dwords to <4 x float>
33 define <4 x float> @f4(<4 x i32> %dwords) {
37 %floats = uitofp <4 x i32> %dwords to <4 x float>
|
| D | vec-strict-conv-01.ll | 25 %dwords = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(<2 x double> %doubles,
27 ret <2 x i64> %dwords
35 %dwords = call <2 x i64> @llvm.experimental.constrained.fptoui.v2i64.v2f64(<2 x double> %doubles,
37 ret <2 x i64> %dwords
41 define <2 x double> @f3(<2 x i64> %dwords) #0 {
45 %doubles = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i64(<2 x i64> %dwords,
52 define <2 x double> @f4(<2 x i64> %dwords) #0 {
56 %doubles = call <2 x double> @llvm.experimental.constrained.uitofp.v2f64.v2i64(<2 x i64> %dwords,
99 %dwords = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(<2 x float> %floats,
101 ret <2 x i64> %dwords
[all …]
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| D | vec-strict-conv-03.ll | 31 define <4 x float> @f3(<4 x i32> %dwords) #0 {
35 %floats = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32> %dwords,
42 define <4 x float> @f4(<4 x i32> %dwords) #0 {
46 %floats = call <4 x float> @llvm.experimental.constrained.uitofp.v4f32.v4i32(<4 x i32> %dwords,
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| /external/mesa3d/src/intel/genxml/ |
| D | gen_pack_header.py | 308 def collect_dwords(self, dwords, start, dim): argument
312 field.collect_dwords(dwords, start + field.start, dim)
315 field.collect_dwords(dwords,
321 if not index in dwords:
322 dwords[index] = self.DWord()
328 dwords[index].fields.append(clone)
332 dwords[index].address = field
339 if index + 1 in dwords and not dwords[index] == dwords[index + 1]:
340 dwords[index].fields.extend(dwords[index + 1].fields)
341 dwords[index].size = 64
[all …]
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| /external/mesa3d/src/freedreno/common/ |
| D | disasm.h | 53 int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage type);
54 int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id);
55 int disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out,
57 int try_disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out, unsigned gpu_id);
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | radeon_common.c | 389 int dwords; in radeon_print_state_atom() local
394 dwords = state->check(&radeon->glCtx, state); in radeon_print_state_atom()
396 fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); in radeon_print_state_atom()
399 if (dwords > state->cmd_size) in radeon_print_state_atom()
400 dwords = state->cmd_size; in radeon_print_state_atom()
401 for (i = 0; i < dwords;) { in radeon_print_state_atom()
408 for (j = 0; j < count && i < dwords; j++) { in radeon_print_state_atom()
424 GLuint dwords = 0; in radeonCountStateEmitSize() local
433 dwords += atom_size; in radeonCountStateEmitSize()
442 dwords += atom_size; in radeonCountStateEmitSize()
[all …]
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| D | r200_state_init.c | 297 BEGIN_BATCH(dwords); \
348 uint32_t dwords = atom->check(ctx, atom); in mtl_emit() local
350 BEGIN_BATCH(dwords); in mtl_emit()
360 uint32_t dwords = atom->check(ctx, atom); in lit_emit() local
362 BEGIN_BATCH(dwords); in lit_emit()
372 uint32_t dwords = atom->check(ctx, atom); in ptp_emit() local
374 BEGIN_BATCH(dwords); in ptp_emit()
384 uint32_t dwords = atom->check(ctx, atom); in veclinear_emit() local
393 uint32_t dwords = atom->check(ctx, atom); in scl_emit() local
395 BEGIN_BATCH(dwords); in scl_emit()
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_common.c | 389 int dwords; in radeon_print_state_atom() local
394 dwords = state->check(&radeon->glCtx, state); in radeon_print_state_atom()
396 fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size); in radeon_print_state_atom()
399 if (dwords > state->cmd_size) in radeon_print_state_atom()
400 dwords = state->cmd_size; in radeon_print_state_atom()
401 for (i = 0; i < dwords;) { in radeon_print_state_atom()
408 for (j = 0; j < count && i < dwords; j++) { in radeon_print_state_atom()
424 GLuint dwords = 0; in radeonCountStateEmitSize() local
433 dwords += atom_size; in radeonCountStateEmitSize()
442 dwords += atom_size; in radeonCountStateEmitSize()
[all …]
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| D | radeon_state_init.c | 264 uint32_t dwords = atom->check(ctx, atom); in scl_emit() local
266 BEGIN_BATCH(dwords); in scl_emit()
276 uint32_t dwords = atom->check(ctx, atom); in vec_emit() local
278 BEGIN_BATCH(dwords); in vec_emit()
288 uint32_t dwords = atom->check(ctx, atom); in lit_emit() local
290 BEGIN_BATCH(dwords); in lit_emit()
300 uint32_t dwords; in check_always_ctx() local
309 dwords = 10; in check_always_ctx()
311 dwords += 6; in check_always_ctx()
313 dwords += 8; in check_always_ctx()
[all …]
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| /external/mesa3d/src/gallium/drivers/freedreno/ |
| D | freedreno_util.h | 240 uint32_t dwords; in __OUT_IB() local
242 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4; in __OUT_IB()
243 assert(dwords > 0); in __OUT_IB()
244 OUT_RING(ring, dwords); in __OUT_IB()
260 uint32_t dwords; in __OUT_IB5() local
262 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4; in __OUT_IB5()
263 assert(dwords > 0); in __OUT_IB5()
264 OUT_RING(ring, dwords); in __OUT_IB5()
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| /external/llvm-project/compiler-rt/lib/builtins/ |
| D | muldi3.c | 18 dwords r; in __muldsi3()
39 dwords x; in __muldi3()
41 dwords y; in __muldi3()
43 dwords r; in __muldi3()
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| /external/compiler-rt/lib/builtins/ |
| D | muldi3.c | 23 dwords r; in __muldsi3()
48 dwords x; in ARM_EABI_FNALIAS()
50 dwords y; in ARM_EABI_FNALIAS()
52 dwords r; in ARM_EABI_FNALIAS()
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| /external/mesa3d/src/freedreno/ir2/ |
| D | disasm-a2xx.c | 214 static int disasm_alu(uint32_t *dwords, uint32_t alu_off, in disasm_alu() argument
217 instr_alu_t *alu = (instr_alu_t *)dwords; in disasm_alu()
222 dwords[0], dwords[1], dwords[2]); in disasm_alu()
456 static int disasm_fetch(uint32_t *dwords, uint32_t alu_off, int level, int sync) in disasm_fetch() argument
458 instr_fetch_t *fetch = (instr_fetch_t *)dwords; in disasm_fetch()
463 dwords[0], dwords[1], dwords[2]); in disasm_fetch()
599 int disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage type) in disasm_a2xx() argument
601 instr_cf_t *cfs = (instr_cf_t *)dwords; in disasm_a2xx()
623 disasm_fetch(dwords + alu_off * 3, alu_off, level, sequence & 0x2); in disasm_a2xx()
625 disasm_alu(dwords + alu_off * 3, alu_off, level, sequence & 0x2, type); in disasm_a2xx()
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| /external/igt-gpu-tools/tests/i915/ |
| D | gem_fence_thrash.c | 126 unsigned int dwords = OBJECT_SIZE >> 2; in _bo_write_verify() local
147 a[dwords - 1] = 0xc0ffee; in _bo_write_verify()
148 igt_assert_f(a[dwords - 1] == 0xc0ffee, in _bo_write_verify()
150 tile_str[t->tiling], a[dwords - 1]); in _bo_write_verify()
152 for (i = 0; i < dwords; i += CACHELINE/sizeof(uint32_t)) { in _bo_write_verify()
166 for (i = 0; i < dwords; i += PAGE_SIZE/sizeof(uint32_t)) { in _bo_write_verify()
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| /external/llvm-project/llvm/docs/AMDGPU/ |
| D | gfx10_addr_mimg.rst | 17 *Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
20 …:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembl…
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| D | gfx7_addr_buf.rst | 15 *Size:* 0, 1 or 2 dwords. Size is controlled by modifiers :ref:`addr64<amdgpu_synid_addr64>`, :ref:…
17 …ddr64<amdgpu_synid_addr64>` is specified, this operand supplies a 64-bit address. Size is 2 dwords.
20 …ffen>` are specified, index is in the first register and offset is in the second. Size is 2 dwords.
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| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| D | etnaviv_disasm.c | 527 print_instr(uint32_t *dwords, int n, enum debug_t debug) in print_instr() argument
529 struct instr *instr = (struct instr *)dwords; in print_instr()
535 printf("%08x %08x %08x %08x ", dwords[0], dwords[1], dwords[2], in print_instr()
536 dwords[3]); in print_instr()
618 etna_disasm(uint32_t *dwords, int sizedwords, enum debug_t debug) in etna_disasm() argument
625 print_instr(&dwords[i], i / 4, debug); in etna_disasm()
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| /external/mesa3d/src/amd/compiler/tests/ |
| D | glsl_scraper.py | 56 self.dwords = None
131 def dwords(f): function
140 self.dwords = list(dwords(io.BytesIO(spirv)))
163 while line_start < len(self.dwords):
165 for i in range(line_start, min(line_start + 6, len(self.dwords))):
166 f.write(' 0x{:08x},'.format(self.dwords[i]))
|