| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | lround-conv-win.ll | 4 ; CHECK: fcvtas w8, s0
15 ; CHECK: fcvtas w0, s0
24 ; CHECK: fcvtas w8, d0
35 ; CHECK: fcvtas w0, d0
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| D | llround-conv.ll | 4 ; CHECK: fcvtas x0, s0
14 ; CHECK: fcvtas x0, s0
23 ; CHECK: fcvtas x0, d0
33 ; CHECK: fcvtas x0, d0
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| D | lround-conv.ll | 4 ; CHECK: fcvtas x0, s0
14 ; CHECK: fcvtas x0, s0
23 ; CHECK: fcvtas x0, d0
33 ; CHECK: fcvtas x0, d0
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| D | lround-conv-fp16.ll | 4 ; CHECK: fcvtas x0, h0
14 ; CHECK: fcvtas x0, h0
24 ; CHECK: fcvtas x0, h0
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| D | llround-conv-fp16.ll | 4 ; CHECK: fcvtas x0, h0
14 ; CHECK: fcvtas x0, h0
24 ; CHECK: fcvtas x0, h0
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| D | lround-conv-fp16-win.ll | 4 ; CHECK: fcvtas w0, h0
14 ; CHECK: fcvtas w0, h0
23 ; CHECK: fcvtas w8, h0
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| D | arm64-cvt.ll | 8 ;CHECK: fcvtas w0, s0
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
16 ;CHECK: fcvtas x0, s0
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
24 ;CHECK: fcvtas w0, d0
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
32 ;CHECK: fcvtas x0, d0
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
[all …]
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| D | fp16_intrinsic_scalar_1op.ll | 17 declare i64 @llvm.aarch64.neon.fcvtas.i64.f16(half)
18 declare i32 @llvm.aarch64.neon.fcvtas.i32.f16(half)
183 ; CHECK: fcvtas w0, h0
186 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f16(half %a)
193 ; CHECK: fcvtas x0, h0
196 %vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f16(half %a)
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| D | round-conv.ll | 244 ; CHECK: fcvtas w0, s0
254 ; CHECK: fcvtas x0, s0
264 ; CHECK: fcvtas w0, d0
274 ; CHECK: fcvtas x0, d0
|
| D | arm64-vcvt.ll | 10 ;CHECK: fcvtas.2s v0, v0
12 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)
20 ;CHECK: fcvtas.4s v0, v0
22 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A)
30 ;CHECK: fcvtas.2d v0, v0
32 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)
39 ;CHECK: fcvtas d0, d0
41 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %A)
45 declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone
46 declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
[all …]
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| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 91 fcvtas h12, h13
92 fcvtas s12, s13
93 fcvtas d21, d14
|
| D | arm64-fp-encoding.s | 254 fcvtas w1, d2
255 fcvtas x1, d2
256 fcvtas w1, s2
257 fcvtas x1, s2
258 fcvtas w1, h2
259 fcvtas x1, h2
261 ; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e]
262 ; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e]
263 ; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e]
264 ; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e]
[all …]
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| D | neon-simd-misc.s | 646 fcvtas v4.4h, v0.4h
647 fcvtas v6.8h, v8.8h
648 fcvtas v6.4s, v8.4s
649 fcvtas v6.2d, v8.2d
650 fcvtas v4.2s, v0.2s
|
| D | fullfp16-neon-neg.s | 230 fcvtas h12, h13
362 fcvtas v4.4h, v0.4h
364 fcvtas v6.8h, v8.8h
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | neon-scalar-cvt.s | 91 fcvtas h12, h13
92 fcvtas s12, s13
93 fcvtas d21, d14
|
| D | arm64-fp-encoding.s | 254 fcvtas w1, d2
255 fcvtas x1, d2
256 fcvtas w1, s2
257 fcvtas x1, s2
258 fcvtas w1, h2
259 fcvtas x1, h2
261 ; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e]
262 ; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e]
263 ; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e]
264 ; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e]
[all …]
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| D | neon-simd-misc.s | 646 fcvtas v4.4h, v0.4h
647 fcvtas v6.8h, v8.8h
648 fcvtas v6.4s, v8.4s
649 fcvtas v6.2d, v8.2d
650 fcvtas v4.2s, v0.2s
|
| D | fullfp16-neon-neg.s | 230 fcvtas h12, h13
362 fcvtas v4.4h, v0.4h
364 fcvtas v6.8h, v8.8h
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-cvt.ll | 8 ;CHECK: fcvtas w0, s0
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
16 ;CHECK: fcvtas x0, s0
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
24 ;CHECK: fcvtas w0, d0
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
32 ;CHECK: fcvtas x0, d0
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
[all …]
|
| D | round-conv.ll | 244 ; CHECK: fcvtas w0, s0
254 ; CHECK: fcvtas x0, s0
264 ; CHECK: fcvtas w0, d0
274 ; CHECK: fcvtas x0, d0
|
| D | arm64-vcvt.ll | 6 ;CHECK: fcvtas.2s v0, v0
8 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)
15 ;CHECK: fcvtas.4s v0, v0
17 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A)
24 ;CHECK: fcvtas.2d v0, v0
26 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)
30 declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone
31 declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
32 declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-scalar-cvt.s.cs | 15 0xac,0xc9,0x21,0x5e = fcvtas s12, s13
16 0xd5,0xc9,0x61,0x5e = fcvtas d21, d14
|
| D | neon-simd-misc.s.cs | 189 0x06,0xc9,0x21,0x4e = fcvtas v6.4s, v8.4s
190 0x06,0xc9,0x61,0x4e = fcvtas v6.2d, v8.2d
191 0x04,0xc8,0x21,0x0e = fcvtas v4.2s, v0.2s
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-fp-aarch64.cc | 272 COMPARE(fcvtas(w0, s1), "fcvtas w0, s1"); in TEST()
273 COMPARE(fcvtas(x2, s3), "fcvtas x2, s3"); in TEST()
274 COMPARE(fcvtas(w4, d5), "fcvtas w4, d5"); in TEST()
275 COMPARE(fcvtas(x6, d7), "fcvtas x6, d7"); in TEST()
348 COMPARE(fcvtas(w0, h1), "fcvtas w0, h1"); in TEST()
349 COMPARE(fcvtas(x2, h3), "fcvtas x2, h3"); in TEST()
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| /external/vixl/doc/ |
| D | changelog.md | 99 `frinta`, `fcvtau` and `fcvtas`.
|