| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_transform.h | 213 struct tgsi_full_immediate immed; in tgsi_transform_immediate_decl() local
216 immed = tgsi_default_full_immediate(); in tgsi_transform_immediate_decl()
217 immed.Immediate.NrTokens = 1 + size; /* one for the token itself */ in tgsi_transform_immediate_decl()
218 immed.u[0].Float = x; in tgsi_transform_immediate_decl()
219 immed.u[1].Float = y; in tgsi_transform_immediate_decl()
220 immed.u[2].Float = z; in tgsi_transform_immediate_decl()
221 immed.u[3].Float = w; in tgsi_transform_immediate_decl()
223 ctx->emit_immediate(ctx, &immed); in tgsi_transform_immediate_decl()
230 struct tgsi_full_immediate immed; in tgsi_transform_immediate_int_decl() local
233 immed = tgsi_default_full_immediate(); in tgsi_transform_immediate_int_decl()
[all …]
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| D | tgsi_lowering.c | 1255 struct tgsi_full_immediate immed; in emit_decls() local
1264 immed = tgsi_default_full_immediate(); in emit_decls()
1265 immed.Immediate.NrTokens = 1 + 4; /* one for the token itself */ in emit_decls()
1266 immed.u[0].Float = 0.0; in emit_decls()
1267 immed.u[1].Float = 1.0; in emit_decls()
1268 immed.u[2].Float = 128.0; in emit_decls()
1269 immed.u[3].Float = 0.0; in emit_decls()
1270 tctx->emit_immediate(tctx, &immed); in emit_decls()
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| /external/mesa3d/src/freedreno/afuc/ |
| D | parser.y | 80 immed(int num) in immed() function
82 instr->immed = num; in immed()
199 | T_OP_NOT reg ',' immediate { new_instr($1); dst($2); immed($4); }
203 new_instr($1); dst($2); immed($4); shift($6);
205 | T_OP_MOV reg ',' immediate { new_instr($1); dst($2); immed($4); }
228 | alu_2src_op reg ',' reg ',' immediate { dst($2); src1($4); immed($6); }
241 src1($2); src2($5); immed($7); bit($10);
248 | branch_op reg ',' immediate ',' T_LABEL_REF { src1($2); immed($4); label($6); }
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| D | asm.c | 180 instr.alui.uimm = ai->immed; in emit_instructions()
201 instr.movi.uimm = ai->immed; in emit_instructions()
250 instr.control.uimm = ai->immed; in emit_instructions()
256 instr.br.bit_or_imm = ai->immed; in emit_instructions()
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| D | asm.h | 44 int immed; member
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| D | disasm.c | 662 bool immed = false; in disasm() local
666 immed = true; in disasm()
669 immed = true; in disasm()
676 if (immed) { in disasm()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedVulcan.td | 214 // Branch, immed
215 // Branch and link, immed
253 // Move immed
303 // Load register, unscaled immed
304 // Load register, immed unprivileged
305 // Load register, unsigned immed
308 // Load register, immed post-index
310 // Load register, immed pre-index
330 // Load pair, immed offset, normal
331 // Load pair, immed offset, signed words, base != SP
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-movi.ll | 7 ; 64-bit immed with 32-bit pattern size, rotated by 0.
14 ; 64-bit immed with 32-bit pattern size, rotated by 2.
21 ; 64-bit immed with 4-bit pattern size, rotated by 3.
28 ; 32-bit immed with 32-bit pattern size, rotated by 16.
35 ; 32-bit immed with 2-bit pattern size, rotated by 1.
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| /external/mesa3d/src/freedreno/ir3/ |
| D | ir3_context.c | 428 struct ir3_instruction *instr, *immed; in create_addr0() local
438 immed = create_immed_typed(block, 1, TYPE_S16); in create_addr0()
439 instr = ir3_SHL_B(block, instr, 0, immed, 0); in create_addr0()
443 immed = create_immed_typed(block, 3, TYPE_S16); in create_addr0()
444 instr = ir3_MULL_U(block, instr, 0, immed, 0); in create_addr0()
448 immed = create_immed_typed(block, 2, TYPE_S16); in create_addr0()
449 instr = ir3_SHL_B(block, instr, 0, immed, 0); in create_addr0()
469 struct ir3_instruction *immed = create_immed_typed(block, const_val, TYPE_S16); in create_addr1() local
470 struct ir3_instruction *instr = ir3_MOV(block, immed, TYPE_S16); in create_addr1()
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| D | instr-a3xx.h | 374 int16_t immed : 16; member
378 int32_t immed : 20; member
382 int32_t immed : 32; member
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| D | ir3.c | 139 cat0->a5xx.immed = instr->cat0.immed; in emit_cat0()
141 cat0->a4xx.immed = instr->cat0.immed; in emit_cat0()
143 cat0->a3xx.immed = instr->cat0.immed; in emit_cat0()
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| /external/mesa3d/src/mesa/state_tracker/ |
| D | st_tgsi_lower_yuv.c | 149 struct tgsi_full_immediate immed; in emit_immed() local
151 immed = tgsi_default_full_immediate(); in emit_immed()
152 immed.Immediate.NrTokens = 1 + 4; /* one for the token itself */ in emit_immed()
153 immed.u[0].Float = x; in emit_immed()
154 immed.u[1].Float = y; in emit_immed()
155 immed.u[2].Float = z; in emit_immed()
156 immed.u[3].Float = w; in emit_immed()
157 tctx->emit_immediate(tctx, &immed); in emit_immed()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX3T110.td | 323 // Load vector pair, immed offset, Q-form [LDP/LDNP].
333 // Load vector pair, immed offset, S/D-form [LDP/LDNP].
632 // Branch, immed
633 // Branch and link, immed
736 // Move immed
850 // Load register, unscaled immed
851 // Load register, immed unprivileged
852 // Load register, unsigned immed
858 // Load register, immed post-index
860 // Load register, immed pre-index
[all …]
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| D | AArch64SchedThunderX2T99.td | 372 // Branch, immed
373 // Branch and link, immed
476 // Move immed
590 // Load register, unscaled immed
591 // Load register, immed unprivileged
592 // Load register, unsigned immed
598 // Load register, immed post-index
600 // Load register, immed pre-index
607 // Load pair, immed offset, normal
608 // Load pair, immed offset, signed words, base != SP
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedThunderX2T99.td | 372 // Branch, immed
373 // Branch and link, immed
476 // Move immed
590 // Load register, unscaled immed
591 // Load register, immed unprivileged
592 // Load register, unsigned immed
598 // Load register, immed post-index
600 // Load register, immed pre-index
607 // Load pair, immed offset, normal
608 // Load pair, immed offset, signed words, base != SP
[all …]
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | arm64-movi.ll | 8 ; 64-bit immed with 32-bit pattern size, rotated by 0.
17 ; 64-bit immed with 32-bit pattern size, rotated by 2.
26 ; 64-bit immed with 4-bit pattern size, rotated by 3.
35 ; 64-bit immed with 64-bit pattern size, many bits.
44 ; 64-bit immed with 64-bit pattern size, one bit.
53 ; 32-bit immed with 32-bit pattern size, rotated by 16.
62 ; 32-bit immed with 2-bit pattern size, rotated by 1.
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| /external/f2fs-tools/tools/sg_write_buffer/include/ |
| D | sg_cmds_basic.h | 170 int sg_ll_start_stop_unit(int sg_fd, bool immed, int pc_mod__fl_num,
179 int sg_ll_sync_cache_10(int sg_fd, bool sync_nv, bool immed, int group,
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| D | u_pstipple.c | 228 struct tgsi_full_immediate *immed) in pstip_transform_immed() argument
233 ctx->emit_immediate(ctx, immed); in pstip_transform_immed()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 297 int immed = MI.getOperand(3).getImm(); in gatherVectorInstructions() local
298 if (immed == 2) { in gatherVectorInstructions()
319 } else if (immed == 0 || immed == 3) { in gatherVectorInstructions()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 295 int immed = MI.getOperand(3).getImm(); in gatherVectorInstructions() local
296 if (immed == 2) { in gatherVectorInstructions()
317 } else if (immed == 0 || immed == 3) { in gatherVectorInstructions()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 295 int immed = MI.getOperand(3).getImm(); in gatherVectorInstructions() local
296 if (immed == 2) { in gatherVectorInstructions()
317 } else if (immed == 0 || immed == 3) { in gatherVectorInstructions()
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| /external/f2fs-tools/tools/sg_write_buffer/ |
| D | sg_cmds_basic2.c | 104 sg_ll_sync_cache_10(int sg_fd, bool sync_nv, bool immed, int group, in sg_ll_sync_cache_10() argument
117 if (immed) in sg_ll_sync_cache_10()
961 sg_ll_start_stop_unit(int sg_fd, bool immed, int pc_mod__fl_num, in sg_ll_start_stop_unit() argument
971 if (immed) in sg_ll_start_stop_unit()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 229 // Move, shift by immed, setflags/no setflags
384 // Load, immed offset
427 // Load, immed pre-indexed (4 cyc for load result, 1 cyc for Base update)
504 // Preload, immed offset
603 // Store, immed offset
629 // Store, immed pre-indexed (1cyc "S, I0/I1", 1cyc writeback)
1116 // ASIMD shift by immed, basic
1120 // ASIMD shift by immed, complex
1125 // ASIMD shift by immed and insert, basic, D-form
1129 // ASIMD shift by immed and insert, basic, Q-form
[all …]
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 218 // Move, shift by immed, setflags/no setflags
377 // Load, immed offset
420 // Load, immed pre-indexed (4 cyc for load result, 1 cyc for Base update)
497 // Preload, immed offset
600 // Store, immed offset
626 // Store, immed pre-indexed (1cyc "S, I0/I1", 1cyc writeback)
1109 // ASIMD shift by immed, basic
1113 // ASIMD shift by immed, complex
1118 // ASIMD shift by immed and insert, basic, D-form
1122 // ASIMD shift by immed and insert, basic, Q-form
[all …]
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| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | cortex-a57-misched-alu.ll | 15 ; ALU, shift by immed - 2 cyc M
|