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/external/arm-trusted-firmware/fdts/
Drtsm_ve-motherboard.dtsi29 interrupts = <0 15 4>;
78 interrupts = <0 11 4>;
86 interrupts = <0 9 4 0 10 4>;
98 interrupts = <0 12 4>;
106 interrupts = <0 13 4>;
114 interrupts = <0 5 4>;
122 interrupts = <0 6 4>;
130 interrupts = <0 7 4>;
138 interrupts = <0 8 4>;
146 interrupts = <0 0 4>;
[all …]
Drtsm_ve-motherboard-aarch32.dtsi30 interrupts = <15>;
79 interrupts = <11>;
87 interrupts = <9 10>;
99 interrupts = <12>;
107 interrupts = <13>;
115 interrupts = <5>;
123 interrupts = <6>;
131 interrupts = <7>;
139 interrupts = <8>;
147 interrupts = <0>;
[all …]
Dfvp-foundation-motherboard.dtsi17 interrupts = <0 15 4>;
66 interrupts = <0 5 4>;
74 interrupts = <0 6 4>;
82 interrupts = <0 7 4>;
90 interrupts = <0 8 4>;
98 interrupts = <0 0 4>;
106 interrupts = <0 2 4>;
114 interrupts = <0 3 4>;
122 interrupts = <0 4 4>;
130 interrupts = <0 0x2a 4>;
Dstm32mp151.dtsi90 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
99 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
108 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
118 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
127 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
136 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
145 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
168 interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
184 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
185 secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
[all …]
Dcorstone700.dtsi43 interrupts = <1 9 0xf08>;
77 interrupts = <0 19 4>;
86 interrupts = <0 20 4>;
93 interrupts = <1 13 0xf08>,
108 interrupts = <0 2 0xf04>;
119 interrupts = <0 12 4>;
131 interrupts = <0 47 4>;
143 interrupts = <0 45 4>;
Dmorello-fvp.dts80 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
86 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
92 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
98 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
104 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
112 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
144 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
Da5ds.dts60 interrupts = <0 84 4>;
93 interrupts = <0 6 0xf04>;
104 interrupts = <1 9 0xf04>;
111 interrupts = <0 8 0xf04>;
120 interrupts = <0 9 0xf04>;
135 interrupts = <0 2 0xf04>;
151 interrupts = <0 43 0xf04>;
Dmorello.dtsi31 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
36 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
46 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
55 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
101 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
Dtc0.dts196 interrupts = <0 317 4>;
240 interrupts = <0x1 0x9 0x4>;
245 interrupts = <0x1 13 0x8>,
275 interrupts = <0x0 116 0x4>;
309 interrupts = <0x0 117 0x4>;
331 interrupts = <0 109 4>;
337 interrupts = <0 197 4>;
345 interrupts = <0 103 4>;
360 interrupts = <0 204 4>;
381 interrupts = <0 107 0x4>,
[all …]
Darm_fpga.dts44 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
52 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
58 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
85 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
100 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
Dn1sdp.dtsi49 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
54 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
64 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
100 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
134 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
146 interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
204 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
Dfvp-base-gicv3-psci-common.dtsi73 /* Number of G0 and G1 secure interrupts defined by the platform */
77 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
153 interrupts = <1 9 4>;
164 interrupts = <1 13 0xff01>,
180 interrupts = <0 26 4>;
187 interrupts = <0 60 4>,
Dfvp-foundation-gicv2-psci.dts98 interrupts = <1 9 0xf04>;
103 interrupts = <1 13 0xff01>,
119 interrupts = <0 26 4>;
126 interrupts = <0 60 4>,
Dfvp-base-gicv2-psci.dts97 interrupts = <1 9 0xf04>;
102 interrupts = <1 13 0xff01>,
118 interrupts = <0 26 4>;
125 interrupts = <0 60 4>,
Dfvp-foundation-gicv3-psci.dts101 interrupts = <1 9 4>;
112 interrupts = <1 13 0xff01>,
128 interrupts = <0 26 4>;
135 interrupts = <0 60 4>,
Dfvp-base-gicv3-psci-aarch32-common.dtsi92 interrupts = <1 9 4>;
103 interrupts = <1 13 0xff01>,
119 interrupts = <0 26 4>;
126 interrupts = <0 60 4>,
Dfvp-base-gicv2-psci-aarch32.dts98 interrupts = <1 9 0xf04>;
103 interrupts = <1 13 0xff01>,
119 interrupts = <0 26 4>;
126 interrupts = <0 60 4>,
Dcorstone700_fpga.dts19 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
28 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
/external/perfetto/src/traced/probes/ftrace/
Dprintk_formats_parser_unittest.cc32 std::string format = R"(0x0 : "Rescheduling interrupts" in TEST()
33 0x0 : "Function call interrupts" in TEST()
34 0x0 : "CPU stop interrupts" in TEST()
35 0x0 : "Timer broadcast interrupts" in TEST()
36 0x0 : "IRQ work interrupts" in TEST()
37 0x0 : "CPU wakeup interrupts" in TEST()
/external/crosvm/devices/src/virtio/vhost/
Dvsock.rs27 interrupts: Option<Vec<Event>>, field
51 let mut interrupts = Vec::new(); in new() localVariable
53 interrupts.push(Event::new().map_err(Error::VhostIrqCreate)?); in new()
61 interrupts: Some(interrupts), in new()
73 interrupts: None, in new_for_testing()
104 if let Some(interrupt) = &self.interrupts { in keep_rds()
161 if let Some(interrupts) = self.interrupts.take() { in activate()
174 interrupts, in activate()
/external/crosvm/aarch64/src/
Dfdt.rs262 let mut interrupts: Vec<u32> = Vec::new(); in create_pci_nodes() localVariable
267 interrupts.push(address.to_config_address(0)); in create_pci_nodes()
268 interrupts.push(0); in create_pci_nodes()
269 interrupts.push(0); in create_pci_nodes()
272 interrupts.push(irq_pin.to_mask() + 1); in create_pci_nodes()
275 interrupts.push(PHANDLE_GIC); in create_pci_nodes()
276 interrupts.push(0); in create_pci_nodes()
277 interrupts.push(0); in create_pci_nodes()
280 interrupts.push(GIC_FDT_IRQ_TYPE_SPI); in create_pci_nodes()
281 interrupts.push(*irq_num); in create_pci_nodes()
[all …]
/external/arm-trusted-firmware/docs/components/
Dexception-handling.rst108 executing in EL3, or has delegated the execution to a lower EL. For interrupts,
117 interrupts. Dispatchers handling such exceptions must therefore explicitly
133 unstacked in strictly the reverse order. For interrupts, the GIC ensures this is
134 the case; for non-interrupts, the |EHF| monitors and asserts this. See
143 top-level handler for interrupts that target EL3, as described in the
147 - On GICv3 systems, when executing in S-EL1, pending Non-secure interrupts of
150 interrupts at S-EL1. Essentially, this deprecates the routing mode described
151 as :ref:`CSS=0, TEL3=0 <EL3 interrupts>`.
153 In order for S-EL1 software to handle Non-secure interrupts while having
154 |EHF| enabled, the dispatcher must adopt a model where Non-secure interrupts
[all …]
/external/arm-trusted-firmware/docs/design/
Dinterrupt-framework-design.rst4 This framework is responsible for managing interrupts routed to EL3. It also
8 #. It should be possible to route interrupts meant to be handled by secure
9 software (Secure interrupts) to EL3, when execution is in non-secure state
13 that secure interrupts are under the control of the secure software with
17 #. It should be possible to route interrupts meant to be handled by
18 non-secure software (Non-secure interrupts) to the last executed exception
64 to the First Exception Level (FEL) capable of handling interrupts. When
84 which ones are valid or invalid. EL3 interrupts are currently supported only
95 Secure-EL1 interrupts
100 control of handling secure interrupts.
[all …]
/external/ltp/testcases/kernel/device-drivers/rtc/
DREADME11 3. Update interrupts test : Sets Update interrupts enable on, waits for five
12 interrupts and then turns it off.
/external/ltp/testcases/kernel/hotplug/cpu_hotplug/functional/
Dcpuhotplug01.sh19 Desc: What happens to disk controller interrupts when offlining CPUs?
147 IRQ_START=$(cat /proc/interrupts)
179 IRQ_END=`cat /proc/interrupts`

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