| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsInstPrinter.cpp | 31 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
241 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsInstPrinter.cpp | 31 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
32 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
226 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
228 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
231 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
235 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
238 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
241 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
244 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
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| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
128 if (Op.isReg()) { in printOperand()
232 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
234 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
237 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
240 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
243 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
246 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
249 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 192 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
195 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
200 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
230 bool isReg() const { return OpKind == MO_Register; } in isReg() function
268 assert(isReg() && "This is not a register operand!"); in getReg()
273 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
278 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
283 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
288 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
293 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 220 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
223 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
228 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
319 bool isReg() const { return OpKind == MO_Register; } in isReg() function
359 assert(isReg() && "This is not a register operand!"); in getReg()
364 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
369 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
374 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
379 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
384 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 220 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
223 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
228 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
319 bool isReg() const { return OpKind == MO_Register; } in isReg() function
359 assert(isReg() && "This is not a register operand!"); in getReg()
364 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
369 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
374 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
379 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
384 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
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| /external/capstone/arch/Mips/ |
| D | MipsInstPrinter.c | 105 static bool isReg(MCInst *MI, unsigned OpNo, unsigned R) in isReg() function
337 if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO)) in printAlias()
339 if (isReg(MI, 1, Mips_ZERO)) in printAlias()
344 if (isReg(MI, 1, Mips_ZERO_64)) in printAlias()
349 if (isReg(MI, 1, Mips_ZERO)) in printAlias()
354 if (isReg(MI, 1, Mips_ZERO_64)) in printAlias()
359 if (isReg(MI, 0, Mips_ZERO)) in printAlias()
364 if (isReg(MI, 0, Mips_FCC0)) in printAlias()
369 if (isReg(MI, 0, Mips_FCC0)) in printAlias()
374 if (isReg(MI, 0, Mips_RA)) in printAlias()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 47 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
59 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
72 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
85 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
97 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
110 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
128 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
146 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
168 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
183 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
[all …]
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| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 115 if (MCOp.isReg()) in getMachineOpValue()
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
153 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
157 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
196 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
228 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
230 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
267 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
295 if (MCOp.isReg() || MCOp.isImm()) in getCallTargetOpValue()
308 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 48 if (MO.isReg() || MO.isImm()) in getDirectBrEncoding()
63 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
76 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
101 assert(MI.getOperand(OpNo).isReg() && "Operand should be a register"); in getVSRpEvenEncoding()
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
124 assert(!MO.isReg() && "Not expecting a register for this operand."); in getImm34Encoding()
154 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
172 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
190 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 112 if (MCOp.isReg()) in getMachineOpValue()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
150 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
227 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| D | LanaiMCCodeEmitter.cpp | 112 if (MCOp.isReg()) in getMachineOpValue()
146 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr()))) in adjustPqBits()
150 assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() && in adjustPqBits()
154 (Op2.isReg() && Op2.getReg() != Lanai::R0))) in adjustPqBits()
193 assert(Op1.isReg() && "First operand is not register."); in getRiMemoryOpValue()
225 assert(Op1.isReg() && "First operand is not register."); in getRrMemoryOpValue()
227 assert(Op2.isReg() && "Second operand is not register."); in getRrMemoryOpValue()
264 assert(Op1.isReg() && "First operand is not register."); in getSplsOpValue()
292 if (MCOp.isReg() || MCOp.isImm()) in getBranchTargetOpValue()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIOptimizeExecMasking.cpp | 68 if (Src.isReg() && in isCopyFromExec()
84 if (Dst.isReg() && in isCopyToExec()
86 MI.getOperand(1).isReg()) in isCopyToExec()
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
114 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
127 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
130 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
183 bool RegSrc = MI.getOperand(1).isReg(); in removeTerminatorBit()
188 bool RegSrc = MI.getOperand(1).isReg(); in removeTerminatorBit()
426 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in runOnMachineFunction()
[all …]
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| D | SIFoldOperands.cpp | 53 assert(FoldOp->isReg() || FoldOp->isGlobal()); in FoldCandidate()
66 bool isReg() const { in isReg() function
190 assert(Old.isReg()); in updateOperand()
397 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
398 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
416 if (!OtherOp.isReg() || in tryAddToFoldList()
498 assert (Sub->isReg()); in getRegSeqInit()
501 SubDef && Sub->isReg() && !Sub->getSubReg() && in getRegSeqInit()
510 if (!Op->isReg()) in getRegSeqInit()
542 if (!OpToFold.isReg()) in tryToFoldACImm()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 62 assert(FoldOp->isReg()); in FoldCandidate()
103 assert(Old.isReg()); in updateOperand()
175 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
176 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
200 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
323 if (!FoldingImm && !OpToFold.isReg()) in runOnMachineFunction()
333 if (OpToFold.isReg() && in runOnMachineFunction()
344 if (Dst.isReg() && in runOnMachineFunction()
372 assert(Fold.OpToFold && Fold.OpToFold->isReg()); in runOnMachineFunction()
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
220 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
239 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
257 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIX16Encoding()
272 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
288 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 171 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
180 if (MO.isReg()) in AddRegOperandsToUseLists()
227 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
229 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
275 if (NewMO->isReg()) { in addOperand()
310 if (Operands[i].isReg()) in RemoveOperand()
315 if (MRI && Operands[OpNo].isReg()) in RemoveOperand()
625 if (!MO.isReg()) { in isIdenticalTo()
692 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
740 if (MO.isReg() && MO.isImplicit()) in getNumExplicitOperands()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 163 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
172 if (MO.isReg()) in AddRegOperandsToUseLists()
219 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
267 if (NewMO->isReg()) { in addOperand()
302 if (Operands[i].isReg()) in RemoveOperand()
307 if (MRI && Operands[OpNo].isReg()) in RemoveOperand()
617 if (!MO.isReg()) { in isIdenticalTo()
684 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
711 if (MO.isReg() && MO.isImplicit()) in getNumExplicitOperands()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIOptimizeExecMasking.cpp | 68 if (Src.isReg() && in isCopyFromExec()
84 if (Dst.isReg() && in isCopyToExec()
86 MI.getOperand(1).isReg()) in isCopyToExec()
111 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
114 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
127 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
130 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO) in isLogicalOpOnExec()
394 if (Src0.isReg() && Src0.getReg() == CopyFromExec) { in runOnMachineFunction()
396 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in runOnMachineFunction()
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| D | SIFoldOperands.cpp | 53 assert(FoldOp->isReg() || FoldOp->isGlobal()); in FoldCandidate()
66 bool isReg() const { in isReg() function
190 assert(Old.isReg()); in updateOperand()
390 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
391 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
409 if (!OtherOp.isReg() || in tryAddToFoldList()
480 assert (Sub->isReg()); in getRegSeqInit()
483 SubDef && Sub->isReg() && !Sub->getSubReg() && in getRegSeqInit()
492 if (!Op->isReg()) in getRegSeqInit()
524 if (!OpToFold.isReg()) in tryToFoldACImm()
[all …]
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 100 assert(isReg() && "Wrong MachineOperand accessor"); in setIsDef()
120 if (!isReg() || !isOnRegUseList()) in removeRegFromUses()
135 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToImmediate()
144 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToFPImmediate()
153 assert((!isReg() || !isTied()) && in ChangeToES()
165 assert((!isReg() || !isTied()) && in ChangeToMCSymbol()
187 bool WasReg = isReg(); in ChangeToRegister()
732 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
741 if (MO.isReg()) in AddRegOperandsToUseLists()
788 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 118 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
286 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) in isCallDependent()
354 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
397 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
463 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
467 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
473 assert(Op1.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
479 assert(Op0.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
538 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
591 if (!MO.isReg()) in canPromoteToNewValueStore()
[all …]
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| D | HexagonExpandCondsets.cpp | 351 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in updateKillFlags()
412 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
519 if (Op.isReg() && Op.isDef() && DefRegs.count(Op)) in updateDeadsInRange()
580 if (SO.isReg()) { in getCondTfrOpcode()
662 bool SameReg = (MS1.isReg() && DR == MS1.getReg()) || in split()
663 (MS2.isReg() && DR == MS2.getReg()); in split()
670 if ((MS1.isReg() && NewSR == MS1.getSubReg()) || in split()
671 (MS2.isReg() && NewSR == MS2.getSubReg())) in split()
695 if (Op.isReg()) in split()
726 if (!Op.isReg() || !Op.isDef()) in isPredicable()
[all …]
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| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
110 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
115 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
117 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
207 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
236 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 108 assert(RI->getOpcode() == Lanai::LDW_RI && RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
110 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
115 RI->getOperand(0).isReg() && in runOnMachineBasicBlock()
117 RI->getOperand(1).isReg() && in runOnMachineBasicBlock()
207 if (!MO.isReg() || !(Reg = MO.getReg())) in delayHasHazard()
236 if (!MO.isReg() || !(Reg = MO.getReg())) in insertDefsUses()
|