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/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64_32-atomics.ll114 declare i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
115 declare i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
116 declare i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
117 declare i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
123 %val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
132 %val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
139 ; CHECK: ldaxr w0, [x0]
141 %val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
148 ; CHECK: ldaxr x0, [x0]
150 %val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
[all …]
Darm64-ldxr-stxr.ll222 %val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
240 %val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
250 ; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
256 ; GISEL: ldaxr w[[LOADVAL:[0-9]+]], [x0]
258 %val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
268 ; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
272 ; GISEL: ldaxr x[[LOADVAL:[0-9]+]], [x0]
274 %val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
280 declare i64 @llvm.aarch64.ldaxr.p0i8(i8*) nounwind
281 declare i64 @llvm.aarch64.ldaxr.p0i16(i16*) nounwind
[all …]
Dfast-isel-cmpxchg.ll6 ; CHECK-NEXT: ldaxr w0, {{\[}}[[ADDR]]{{\]}}
31 ; CHECK-NEXT: ldaxr w0, {{\[}}[[ADDR]]{{\]}}
55 ; CHECK-NEXT: ldaxr x0, {{\[}}[[ADDR]]{{\]}}
Dcmpxchg-idioms.ll9 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
65 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
102 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x19]
Dcmpxchg-O0.ll43 ; CHECK: ldaxr [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}}
60 ; CHECK: ldaxr [[OLD:x[0-9]+]], {{\[}}[[ADDR]]{{\]}}
Darm64-atomic.ll9 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
28 ; CHECK-NEXT: ldaxr w[[RESULT:[0-9]+]], [x0]
50 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
101 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
116 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
Datomic-ops.ll203 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
232 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
319 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
348 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
432 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
544 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
680 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
817 ; OUTLINE_ATOMICS-NEXT: ldaxr x8, [x9]
831 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
1087 ; OUTLINE_ATOMICS-NEXT: ldaxr w8, [x9]
[all …]
Datomic-ops-lse.ll455 ; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
482 ; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
509 ; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
534 ; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
613 ; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
640 ; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
667 ; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
692 ; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
773 ; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
800 ; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-ldxr-stxr.ll179 %val = call i64 @llvm.aarch64.ldaxr.p0i8(i8* %addr)
193 %val = call i64 @llvm.aarch64.ldaxr.p0i16(i16* %addr)
202 ; CHECK: ldaxr w[[LOADVAL:[0-9]+]], [x0]
207 %val = call i64 @llvm.aarch64.ldaxr.p0i32(i32* %addr)
216 ; CHECK: ldaxr x[[LOADVAL:[0-9]+]], [x0]
219 %val = call i64 @llvm.aarch64.ldaxr.p0i64(i64* %addr)
225 declare i64 @llvm.aarch64.ldaxr.p0i8(i8*) nounwind
226 declare i64 @llvm.aarch64.ldaxr.p0i16(i16*) nounwind
227 declare i64 @llvm.aarch64.ldaxr.p0i32(i32*) nounwind
228 declare i64 @llvm.aarch64.ldaxr.p0i64(i64*) nounwind
Dcmpxchg-idioms.ll7 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
62 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
Dcmpxchg-O0.ll36 ; CHECK: ldaxr [[OLD:w[0-9]+]], [x0]
51 ; CHECK: ldaxr [[OLD:x[0-9]+]], [x0]
Darm64-atomic.ll7 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]]
25 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
44 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x[[ADDR]]
94 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
108 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
Datomic-ops.ll143 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
163 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
223 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
243 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
303 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
383 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
480 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
573 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
743 ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
767 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dselect-ldaxr-intrin.mir28 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load …
50 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load …
72 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load …
92 …%1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load …
/external/llvm-project/llvm/test/Transforms/AtomicExpand/AArch64/
Dexpand-atomicrmw-xchg-fp.ll9 ; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.aarch64.ldaxr.p0f16(half* [[PTR:%.*]])
32 ; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.aarch64.ldaxr.p0f32(float* [[PTR:%.*]])
55 ; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.aarch64.ldaxr.p0f64(double* [[PTR:%.*]])
/external/arm-trusted-firmware/lib/locks/exclusive/aarch64/
Dspinlock.S54 l2: ldaxr w1, [x0]
/external/llvm/test/MC/AArch64/
Darm64-memory.s510 ldaxr w2, [x4]
511 ldaxr x2, [x4]
517 ; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
518 ; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-memory.s510 ldaxr w2, [x4]
511 ldaxr x2, [x4]
517 ; CHECK: ldaxr w2, [x4] ; encoding: [0x82,0xfc,0x5f,0x88]
518 ; CHECK: ldaxr x2, [x4] ; encoding: [0x82,0xfc,0x5f,0xc8]
Dbasic-a64-instructions.s2279 ldaxr wzr, [x22]
2280 ldaxr x21, [x23]
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-memory.txt498 # CHECK: ldaxr w2, [x4]
499 # CHECK: ldaxr x2, [x4]
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darm64-memory.txt498 # CHECK: ldaxr w2, [x4]
499 # CHECK: ldaxr x2, [x4]
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s874 ldaxr w6, [sp] label
875 ldaxr x5, [x6] label
876 ldaxr x5, [x6] label
877 ldaxr x5, [x6] label
2131 # CHECK-NEXT: 1 3 1.00 * * U ldaxr w6, [sp]
2132 # CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6]
2133 # CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6]
2134 # CHECK-NEXT: 1 3 1.00 * * U ldaxr x5, [x6]
3314 … - - - - - - - - - 1.00 - - ldaxr w6, [sp]
3315 … - - - - - - - - - 1.00 - - ldaxr x5, [x6]
[all …]
/external/vixl/
DREADME.md125 `stlxrh`, `stlxr`, `ldaxrb`, `ldaxrh`, `ldaxr`, `stlxp`, `ldaxp`, `stlrb`,
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc1607 COMPARE(ldaxr(w21, MemOperand(x22)), "ldaxr w21, [x22]"); in TEST()
1608 COMPARE(ldaxr(w23, MemOperand(sp)), "ldaxr w23, [sp]"); in TEST()
1609 COMPARE(ldaxr(x24, MemOperand(x25)), "ldaxr x24, [x25]"); in TEST()
1610 COMPARE(ldaxr(x26, MemOperand(sp)), "ldaxr x26, [sp]"); in TEST()
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs894 0xdf,0xfe,0x5f,0x88 = ldaxr wzr, [x22]
895 0xf5,0xfe,0x5f,0xc8 = ldaxr x21, [x23]

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