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/external/llvm-project/llvm/test/MC/Mips/
Dset-at-directive.s10 # CHECK: lw $2, 0($1)
12 lw $2, 65536($2)
16 # CHECK: lw $1, 0($2)
18 lw $1, 65536($1)
22 # CHECK: lw $1, 0($3)
24 lw $1, 65536($1)
28 # CHECK: lw $1, 0($4)
30 lw $1, 65536($1)
34 # CHECK: lw $1, 0($5)
36 lw $1, 65536($1)
[all …]
Dmemory-offsets.s9 …lw $31, ($29) # CHECK: lw $ra, 0($sp) # encoding: [0x8f,0xbf,0x00,0x00]
10 …lw $31, 0($29) # CHECK: lw $ra, 0($sp) # encoding: [0x8f,0xbf,0x00,0x00]
11 …lw $31, (8)($29) # CHECK: lw $ra, 8($sp) # encoding: [0x8f,0xbf,0x00,0x08]
12 …lw $31, 3 + (4 * 8)($29) # CHECK: lw $ra, 35($sp) # encoding: [0x8f,0xbf,0x00,0x23]
13 …lw $31, (8 + 8)($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
14 …lw $31, (8 << 4)($29) # CHECK: lw $ra, 128($sp) # encoding: [0x8f,0xbf,0x00,0x80]
15 …lw $31, (32768 >> 2)($29) # CHECK: lw $ra, 8192($sp) # encoding: [0x8f,0xbf,0x20,0x00]
16 …lw $31, 32768 >> 2($29) # CHECK: lw $ra, 8192($sp) # encoding: [0x8f,0xbf,0x20,0x00]
17 …lw $31, 2 << 3($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
18 …lw $31, (2 << 3)($29) # CHECK: lw $ra, 16($sp) # encoding: [0x8f,0xbf,0x00,0x10]
[all …]
Dexpr1.s10 # 32R2-EL: lw $4, %lo(foo)($4) # encoding: [A,A,0x84,0x8c]
12 # 32R2-EL: lw $4, 56($4) # encoding: [0x38,0x00,0x84,0x8c]
16 # 32R2-EL: lw $4, %lo(foo+(%lo(8)))($1) # encoding: [A,A,0x24,0x8c]
18 # 32R2-EL: lw $4, %lo(12+foo)($4) # encoding: [A,A,0x84,0x8c]
20 # 32R2-EL: lw $4, %lo(16+foo)($4) # encoding: [A,A,0x84,0x8c]
22 # 32R2-EL: lw $4, 10($4) # encoding: [0x0a,0x00,0x84,0x8c]
23 # 32R2-EL: lw $4, 15($4) # encoding: [0x0f,0x00,0x84,0x8c]
24 # 32R2-EL: lw $4, 21($4) # encoding: [0x15,0x00,0x84,0x8c]
25 # 32R2-EL: lw $4, 28($4) # encoding: [0x1c,0x00,0x84,0x8c]
26 # 32R2-EL: lw $4, 6($4) # encoding: [0x06,0x00,0x84,0x8c]
[all …]
Dmacro-ld-sd.s14 # 32: lw $8, 0($5) # encoding: [0x8c,0xa8,0x00,0x00]
15 # 32: lw $9, 4($5) # encoding: [0x8c,0xa9,0x00,0x04]
16 # MM2: lw $8, 0($5) # encoding: [0xfd,0x05,0x00,0x00]
17 # MM2: lw $9, 4($5) # encoding: [0xfd,0x25,0x00,0x04]
18 # MM6: lw $8, 0($5) # encoding: [0xfd,0x05,0x00,0x00]
19 # MM6: lw $9, 4($5) # encoding: [0xfd,0x25,0x00,0x04]
30 # 32: lw $9, 4($8) # encoding: [0x8d,0x09,0x00,0x04]
31 # 32: lw $8, 0($8) # encoding: [0x8d,0x08,0x00,0x00]
32 # MM2: lw $9, 4($8) # encoding: [0xfd,0x28,0x00,0x04]
33 # MM2: lw $8, 0($8) # encoding: [0xfd,0x08,0x00,0x00]
[all …]
/external/llvm/test/MC/Mips/
Dset-at-directive.s10 # CHECK: lw $2, 0($1)
12 lw $2, 65536($2)
16 # CHECK: lw $1, 0($2)
18 lw $1, 65536($1)
22 # CHECK: lw $1, 0($3)
24 lw $1, 65536($1)
28 # CHECK: lw $1, 0($4)
30 lw $1, 65536($1)
34 # CHECK: lw $1, 0($5)
36 lw $1, 65536($1)
[all …]
Dexpr1.s10 # 32R2-EL: lw $4, %lo(foo)($4) # encoding: [A,A,0x84,0x8c]
12 # 32R2-EL: lw $4, 56($4) # encoding: [0x38,0x00,0x84,0x8c]
13 # 32R2-EL: lw $4, %lo(8+foo)($4) # encoding: [A,A,0x84,0x8c]
15 # 32R2-EL: lw $4, %lo(8+foo)($4) # encoding: [A,A,0x84,0x8c]
17 # 32R2-EL: lw $4, %lo(8+foo)($4) # encoding: [A,A,0x84,0x8c]
19 # 32R2-EL: lw $4, 10($4) # encoding: [0x0a,0x00,0x84,0x8c]
20 # 32R2-EL: lw $4, 15($4) # encoding: [0x0f,0x00,0x84,0x8c]
21 # 32R2-EL: lw $4, 21($4) # encoding: [0x15,0x00,0x84,0x8c]
22 # 32R2-EL: lw $4, 28($4) # encoding: [0x1c,0x00,0x84,0x8c]
23 # 32R2-EL: lw $4, %lo(65542)($4) # encoding: [0x06,0x00,0x84,0x8c]
[all …]
/external/llvm-project/llvm/test/CodeGen/RISCV/
Dcallee-saved-gprs.ll46 ; RV32I-NEXT: lw a0, %lo(var)(a7)
48 ; RV32I-NEXT: lw a0, %lo(var+4)(a7)
50 ; RV32I-NEXT: lw a0, %lo(var+8)(a7)
52 ; RV32I-NEXT: lw a0, %lo(var+12)(a7)
55 ; RV32I-NEXT: lw a0, 16(a5)
57 ; RV32I-NEXT: lw a0, 20(a5)
59 ; RV32I-NEXT: lw t4, 24(a5)
60 ; RV32I-NEXT: lw t5, 28(a5)
61 ; RV32I-NEXT: lw t6, 32(a5)
62 ; RV32I-NEXT: lw s2, 36(a5)
[all …]
Dstack-store-check.ll32 ; CHECK-NEXT: lw s6, %lo(U)(a0)
33 ; CHECK-NEXT: lw s7, %lo(U+4)(a0)
34 ; CHECK-NEXT: lw s8, %lo(U+8)(a0)
35 ; CHECK-NEXT: lw s0, %lo(U+12)(a0)
48 ; CHECK-NEXT: lw s3, 616(sp)
49 ; CHECK-NEXT: lw s4, 620(sp)
50 ; CHECK-NEXT: lw s9, 624(sp)
51 ; CHECK-NEXT: lw s11, 628(sp)
64 ; CHECK-NEXT: lw a0, 568(sp)
66 ; CHECK-NEXT: lw a0, 572(sp)
[all …]
Dinterrupt-attr-nocall.ll32 ; CHECK-RV32-NEXT: lw a0, %lo(a)(a0)
34 ; CHECK-RV32-NEXT: lw a1, %lo(b)(a1)
38 ; CHECK-RV32-NEXT: lw a1, 8(sp)
39 ; CHECK-RV32-NEXT: lw a0, 12(sp)
49 ; CHECK-RV32IF-NEXT: lw a0, %lo(a)(a0)
51 ; CHECK-RV32IF-NEXT: lw a1, %lo(b)(a1)
55 ; CHECK-RV32IF-NEXT: lw a1, 8(sp)
56 ; CHECK-RV32IF-NEXT: lw a0, 12(sp)
66 ; CHECK-RV32IFD-NEXT: lw a0, %lo(a)(a0)
68 ; CHECK-RV32IFD-NEXT: lw a1, %lo(b)(a1)
[all …]
Dfp128.ll17 ; RV32I-NEXT: lw a6, %lo(x)(a0)
18 ; RV32I-NEXT: lw a7, %lo(x+4)(a0)
19 ; RV32I-NEXT: lw a3, %lo(x+8)(a0)
20 ; RV32I-NEXT: lw a0, %lo(x+12)(a0)
22 ; RV32I-NEXT: lw a5, %lo(y)(a4)
23 ; RV32I-NEXT: lw a2, %lo(y+4)(a4)
24 ; RV32I-NEXT: lw a1, %lo(y+8)(a4)
25 ; RV32I-NEXT: lw a4, %lo(y+12)(a4)
38 ; RV32I-NEXT: lw ra, 44(sp)
54 ; RV32I-NEXT: lw a6, %lo(x)(a0)
[all …]
Dremat.ll41 ; RV32I-NEXT: lw a0, %lo(a)(s6)
58 ; RV32I-NEXT: lw a0, %lo(a)(s6)
64 ; RV32I-NEXT: lw a1, %lo(l)(s2)
68 ; RV32I-NEXT: lw a1, %lo(b)(s11)
69 ; RV32I-NEXT: lw a2, %lo(c)(s10)
70 ; RV32I-NEXT: lw a3, %lo(d)(s1)
71 ; RV32I-NEXT: lw a4, %lo(e)(s0)
76 ; RV32I-NEXT: lw a0, %lo(k)(s3)
80 ; RV32I-NEXT: lw a0, %lo(b)(s11)
81 ; RV32I-NEXT: lw a1, %lo(c)(s10)
[all …]
/external/llvm/test/CodeGen/Mips/
Dhf16_1.ll168 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_1)(${{[0-9]+}})
169 ; 2: lw ${{[0-9]+}}, %call16(v_sf)(${{[0-9]+}})
171 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_2)(${{[0-9]+}})
172 ; 2: lw ${{[0-9]+}}, %call16(v_df)(${{[0-9]+}})
174 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_5)(${{[0-9]+}})
175 ; 2: lw ${{[0-9]+}}, %call16(v_sf_sf)(${{[0-9]+}})
177 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_6)(${{[0-9]+}})
178 ; 2: lw ${{[0-9]+}}, %call16(v_df_sf)(${{[0-9]+}})
180 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_10)(${{[0-9]+}})
181 ; 2: lw ${{[0-9]+}}, %call16(v_df_df)(${{[0-9]+}})
[all …]
Dinlineasm_constraint_ZC.ll11 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
25 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
27 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
29 ; ALL: lw $1, -4($[[BASEPTR]])
39 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
41 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
43 ; ALL: lw $1, 4($[[BASEPTR]])
53 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
[all …]
Dinterrupt-attr.ll38 ; CHECK: lw $26, [[R4:[0-9]+]]($sp)
40 ; CHECK: lw $26, [[R3:[0-9]+]]($sp)
42 ; CHECK: lw $1, {{[0-9]+}}($sp)
43 ; CHECK: lw $gp, {{[0-9]+}}($sp)
44 ; CHECK: lw $ra, [[R5:[0-9]+]]($sp)
45 ; CHECK: lw $8, {{[0-9]+}}($sp)
46 ; CHECK: lw $9, {{[0-9]+}}($sp)
47 ; CHECK: lw $10, {{[0-9]+}}($sp)
48 ; CHECK: lw $11, {{[0-9]+}}($sp)
49 ; CHECK: lw $12, {{[0-9]+}}($sp)
[all …]
Dinlineasm_constraint_R.ll9 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
23 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
37 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
51 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dhf16_1.ll168 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_1)(${{[0-9]+}})
169 ; 2: lw ${{[0-9]+}}, %call16(v_sf)(${{[0-9]+}})
171 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_2)(${{[0-9]+}})
172 ; 2: lw ${{[0-9]+}}, %call16(v_df)(${{[0-9]+}})
174 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_5)(${{[0-9]+}})
175 ; 2: lw ${{[0-9]+}}, %call16(v_sf_sf)(${{[0-9]+}})
177 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_6)(${{[0-9]+}})
178 ; 2: lw ${{[0-9]+}}, %call16(v_df_sf)(${{[0-9]+}})
180 ; 1: lw ${{[0-9]+}}, %got(__mips16_call_stub_10)(${{[0-9]+}})
181 ; 2: lw ${{[0-9]+}}, %call16(v_df_df)(${{[0-9]+}})
[all …]
Dinlineasm-constraint-ZC-1.ll11 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
13 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
15 ; ALL: lw $1, 0($[[BASEPTR]])
25 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
27 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
29 ; ALL: lw $1, -4($[[BASEPTR]])
39 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
41 ; ALL: lw $[[BASEPTR:[0-9]+]], %got(data)(
43 ; ALL: lw $1, 4($[[BASEPTR]])
53 …call void asm sideeffect "lw $$1, $0", "*^ZC,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [81…
[all …]
Dinterrupt-attr.ll38 ; CHECK: lw $26, [[R4:[0-9]+]]($sp)
40 ; CHECK: lw $26, [[R3:[0-9]+]]($sp)
42 ; CHECK: lw $1, {{[0-9]+}}($sp)
43 ; CHECK: lw $gp, {{[0-9]+}}($sp)
44 ; CHECK: lw $ra, [[R5:[0-9]+]]($sp)
45 ; CHECK: lw $8, {{[0-9]+}}($sp)
46 ; CHECK: lw $9, {{[0-9]+}}($sp)
47 ; CHECK: lw $10, {{[0-9]+}}($sp)
48 ; CHECK: lw $11, {{[0-9]+}}($sp)
49 ; CHECK: lw $12, {{[0-9]+}}($sp)
[all …]
Dgprestore.ll25 ; O32-NEXT: lw $25, %call16(f1)($16)
28 ; O32-NEXT: lw $1, %got(p)($16)
29 ; O32-NEXT: lw $4, 0($1)
30 ; O32-NEXT: lw $25, %call16(f2)($16)
33 ; O32-NEXT: lw $1, %got(q)($16)
34 ; O32-NEXT: lw $17, 0($1)
35 ; O32-NEXT: lw $25, %call16(f2)($16)
38 ; O32-NEXT: lw $1, %got(r)($16)
39 ; O32-NEXT: lw $5, 0($1)
40 ; O32-NEXT: lw $25, %call16(f3)($16)
[all …]
Do32_cc_byval.ll24 ; CHECK-NEXT: lw $17, %got(f1.s1)($16)
26 ; CHECK-NEXT: lw $1, 12($18)
27 ; CHECK-NEXT: lw $2, 16($18)
28 ; CHECK-NEXT: lw $3, 20($18)
29 ; CHECK-NEXT: lw $4, 24($18)
30 ; CHECK-NEXT: lw $5, 28($18)
36 ; CHECK-NEXT: lw $1, 8($18)
38 ; CHECK-NEXT: lw $6, %lo(f1.s1)($17)
39 ; CHECK-NEXT: lw $7, 4($18)
40 ; CHECK-NEXT: lw $1, %got($CPI0_0)($16)
[all …]
Dinlineasm-constraint-R.ll9 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
11 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
13 ; CHECK: lw $1, 0($[[BASEPTR]])
23 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
25 ; CHECK: lw $[[BASEPTR:[0-9]+]], %got(data)(
27 ; CHECK: lw $1, 4($[[BASEPTR]])
37 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
39 ; CHECK-DAG: lw $[[BASEPTR:[0-9]+]], %got(data)(
41 ; CHECK: lw $1, 252($[[BASEPTR]])
51 …call void asm sideeffect "lw $$1, $0", "*R,~{$1}"(i32* getelementptr inbounds ([8193 x i32], [8193…
[all …]
/external/eigen/bench/btl/data/
Dperlib_plot_settings.txt1 eigen3 ; with lines lw 4 lt 1 lc rgbcolor "black"
2 eigen2 ; with lines lw 3 lt 1 lc rgbcolor "#999999"
3 EigenBLAS ; with lines lw 3 lt 3 lc rgbcolor "#999999"
4 eigen3_novec ; with lines lw 2 lt 1 lc rgbcolor "#999999"
5 eigen3_nogccvec ; with lines lw 2 lt 2 lc rgbcolor "#991010"
6 INTEL_MKL ; with lines lw 3 lt 1 lc rgbcolor "#ff0000"
7 ATLAS ; with lines lw 3 lt 1 lc rgbcolor "#008000"
8 gmm ; with lines lw 3 lt 1 lc rgbcolor "#0000ff"
9 ublas ; with lines lw 3 lt 1 lc rgbcolor "#00b7ff"
10 mtl4 ; with lines lw 3 lt 1 lc rgbcolor "#d18847"
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/
Dicmpa.ll21 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
22 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
23 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
24 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
42 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
43 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
44 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
45 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
63 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
64 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dicmpa.ll21 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
22 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
23 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
24 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
42 ; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
43 ; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
44 ; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
45 ; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
63 ; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
64 ; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
[all …]
/external/llvm-project/compiler-rt/lib/xray/
Dxray_trampoline_mips.S38 lw $t9, 0($t9)
52 lw $a0, 16($sp)
53 lw $a1, 20($sp)
54 lw $a2, 24($sp)
55 lw $a3, 28($sp)
56 lw $ra, 32($sp)
85 lw $t9, 0($t9)
99 lw $v0, 16($sp)
100 lw $v1, 20($sp)
101 lw $a0, 24($sp)
[all …]

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