Home
last modified time | relevance | path

Searched refs:lwl (Results 1 – 25 of 126) sorted by relevance

123456

/external/llvm-project/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll28 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
31 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
37 ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
40 ; MIPS64R2-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
43 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
46 ; MIPS64R2-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
92 ; MIPS32-EL: lwl $2, 3($[[R1:[0-9]+]])
94 ; MIPS32-EL: lwl $3, 7($[[R1:[0-9]+]])
97 ; MIPS32-EB: lwl $2, 0($[[R1:[0-9]+]])
99 ; MIPS32-EB: lwl $3, 4($[[R1:[0-9]+]])
[all …]
Dunalignedload.ll43 ; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[R2]])
53 ; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[R2]])
/external/llvm/test/CodeGen/Mips/
Dload-store-left-right.ll28 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
31 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
37 ; MIPS64-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
40 ; MIPS64-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
80 ; MIPS32-EL: lwl $2, 3($[[R1:[0-9]+]])
82 ; MIPS32-EL: lwl $3, 7($[[R1:[0-9]+]])
85 ; MIPS32-EB: lwl $2, 0($[[R1:[0-9]+]])
87 ; MIPS32-EB: lwl $3, 4($[[R1:[0-9]+]])
111 ; MIPS32-EL: lwl $[[R0:[0-9]+]], 3($[[R1:[0-9]+]])
114 ; MIPS32-EB: lwl $[[R0:[0-9]+]], 0($[[R1:[0-9]+]])
[all …]
Dunalignedload.ll43 ; MIPS32-EL-DAG: lwl $[[R1:4]], 3($[[R2]])
53 ; MIPS32-EB-DAG: lwl $[[R1:4]], 0($[[R2]])
/external/llvm/test/MC/Mips/
Dmips-expansions.s545 # CHECK-BE: lwl $8, 0($zero) # encoding: [0x88,0x08,0x00,0x00]
547 # CHECK-LE: lwl $8, 3($zero) # encoding: [0x03,0x00,0x08,0x88]
551 # CHECK-BE: lwl $8, 2($zero) # encoding: [0x88,0x08,0x00,0x02]
553 # CHECK-LE: lwl $8, 5($zero) # encoding: [0x05,0x00,0x08,0x88]
558 # CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
561 # CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
565 # CHECK-BE: lwl $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00]
567 # CHECK-LE: lwl $8, -32765($zero) # encoding: [0x03,0x80,0x08,0x88]
572 # CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
575 # CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
[all …]
Dmicromips-loadstore-unaligned.s12 # CHECK-EL: lwl $4, 16($5) # encoding: [0x85,0x60,0x10,0x00]
19 # CHECK-EB: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10]
23 lwl $4, 16($5)
Dmips64-expansions.s199 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
209 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
218 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
228 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
238 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
249 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
259 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
270 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
Dsym-offset.ll12 ; check that the immediate fields of lwl and lwr are three apart.
13 ; 8841000e lwl at,14(v0)
Dnacl-mask.s51 lwl $4, 0($9)
90 # CHECK-NEXT: lwl $4, 0($9)
/external/llvm-project/llvm/test/MC/Mips/
Dmicromips-loadstore-unaligned.s12 # CHECK-EL: lwl $4, 16($5) # encoding: [0x85,0x60,0x10,0x00]
19 # CHECK-EB: lwl $4, 16($5) # encoding: [0x60,0x85,0x00,0x10]
23 lwl $4, 16($5)
Dmips-expansions.s700 # CHECK-BE: lwl $8, 0($zero) # encoding: [0x88,0x08,0x00,0x00]
702 # CHECK-LE: lwl $8, 3($zero) # encoding: [0x03,0x00,0x08,0x88]
706 # CHECK-BE: lwl $8, 2($zero) # encoding: [0x88,0x08,0x00,0x02]
708 # CHECK-LE: lwl $8, 5($zero) # encoding: [0x05,0x00,0x08,0x88]
713 # CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
716 # CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
720 # CHECK-BE: lwl $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00]
722 # CHECK-LE: lwl $8, -32765($zero) # encoding: [0x03,0x80,0x08,0x88]
727 # CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
730 # CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
[all …]
Dsym-offset.ll12 ; check that the immediate fields of lwl and lwr are three apart.
13 ; 8841000e lwl at,14(v0)
Dmips64-expansions.s202 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
212 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
221 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
231 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
241 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
252 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
262 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
273 # CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
Dnacl-mask.s51 lwl $4, 0($9)
90 # CHECK-NEXT: lwl $4, 0($9)
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/
Dload_split_because_of_memsize_or_align.ll35 ; MIPS32-NEXT: lwl $1, 3($4)
61 ; MIPS32-NEXT: lwl $1, 3($4)
135 ; MIPS32-NEXT: lwl $2, 3($4)
163 ; MIPS32-NEXT: lwl $2, 3($4)
243 ; MIPS32-NEXT: lwl $2, 3($4)
246 ; MIPS32-NEXT: lwl $1, 7($4)
273 ; MIPS32-NEXT: lwl $2, 3($4)
353 ; MIPS32-NEXT: lwl $2, 3($4)
356 ; MIPS32-NEXT: lwl $1, 7($4)
387 ; MIPS32-NEXT: lwl $2, 3($4)
[all …]
Dload_4_unaligned.ll20 ; MIPS32-NEXT: lwl $1, 3($2)
43 ; MIPS32-NEXT: lwl $1, 3($2)
106 ; MIPS32-NEXT: lwl $2, 3($1)
128 ; MIPS32-NEXT: lwl $2, 3($1)
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
Dldr_str.ll16 ; MIPS32R5-EB-NEXT: lwl $2, 20($5)
19 ; MIPS32R5-EB-NEXT: lwl $1, 16($5)
30 ; MIPS32R5-EL-NEXT: lwl $2, 19($5)
33 ; MIPS32R5-EL-NEXT: lwl $1, 23($5)
77 ; MIPS32R5-EB-NEXT: lwl $1, 16($5)
87 ; MIPS32R5-EL-NEXT: lwl $1, 19($5)
/external/capstone/suite/MC/Mips/
Dmicromips-loadstore-unaligned.s.cs2 0x85,0x60,0x10,0x00 = lwl $a0, 16($a1)
Dmicromips-loadstore-unaligned-EB.s.cs2 0x60,0x85,0x00,0x10 = lwl $a0, 16($a1)
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips1-wrong-error.s10 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
Dinvalid-mips3-wrong-error.s16 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm-project/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips1-wrong-error.s10 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
Dinvalid-mips3-wrong-error.s16 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm-project/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1-wrong-error.s10 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1-wrong-error.s10 …lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instructi…

123456