| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_winsys.h | 198 struct radeon_cmdbuf { struct
327 void *(*buffer_map)(struct pb_buffer *buf, struct radeon_cmdbuf *cs,
490 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys_ctx *ctx, enum ring_type ring_type,
509 struct radeon_cmdbuf *(*cs_add_parallel_compute_ib)(struct radeon_cmdbuf *cs,
519 bool (*cs_setup_preemption)(struct radeon_cmdbuf *cs, const uint32_t *preamble_ib,
527 void (*cs_destroy)(struct radeon_cmdbuf *cs);
540 unsigned (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf,
554 int (*cs_lookup_buffer)(struct radeon_cmdbuf *cs, struct pb_buffer *buf);
564 bool (*cs_validate)(struct radeon_cmdbuf *cs);
576 bool (*cs_check_space)(struct radeon_cmdbuf *cs, unsigned dw, bool force_chaining);
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| D | radeon_video.h | 60 bool si_vid_resize_buffer(struct pipe_screen *screen, struct radeon_cmdbuf *cs,
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_cs.h | 35 struct radeon_cmdbuf *cs, in radeon_check_space()
43 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
52 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
58 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
67 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
74 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, in radeon_set_context_reg_idx()
85 static inline void radeon_set_context_reg_rmw(struct radeon_cmdbuf *cs, in radeon_set_context_reg_rmw()
97 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
106 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
113 struct radeon_cmdbuf *cs, in radeon_set_sh_reg_idx()
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| D | radv_radeon_winsys.h | 98 struct radeon_cmdbuf { struct
272 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws,
275 void (*cs_destroy)(struct radeon_cmdbuf *cs);
277 void (*cs_reset)(struct radeon_cmdbuf *cs);
279 VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
281 void (*cs_grow)(struct radeon_cmdbuf * cs, size_t min_size);
285 struct radeon_cmdbuf **cs_array,
287 struct radeon_cmdbuf *initial_preamble_cs,
288 struct radeon_cmdbuf *continue_preamble_cs,
294 void (*cs_add_buffer)(struct radeon_cmdbuf *cs,
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| D | radv_sqtt.c | 66 struct radeon_cmdbuf *cs, in radv_emit_thread_trace_start()
233 struct radeon_cmdbuf *cs, in radv_copy_thread_trace_info_regs()
270 struct radeon_cmdbuf *cs, in radv_emit_thread_trace_stop()
346 struct radeon_cmdbuf *cs, in radv_emit_thread_trace_userdata()
369 struct radeon_cmdbuf *cs, bool enable) in radv_emit_spi_config_cntl()
391 struct radeon_cmdbuf *cs, int family) in radv_emit_wait_for_idle()
557 struct radeon_cmdbuf *cs = queue->device->thread_trace_start_cs[family]; in radv_begin_thread_trace()
565 struct radeon_cmdbuf *cs = queue->device->thread_trace_stop_cs[family]; in radv_end_thread_trace()
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| D | radv_private.h | 726 struct radeon_cmdbuf *initial_preamble_cs;
727 struct radeon_cmdbuf *initial_full_flush_preamble_cs;
728 struct radeon_cmdbuf *continue_preamble_cs;
776 struct radeon_cmdbuf *empty_cs[RADV_MAX_QUEUE_FAMILIES];
843 struct radeon_cmdbuf *thread_trace_start_cs[2];
844 struct radeon_cmdbuf *thread_trace_stop_cs[2];
1432 struct radeon_cmdbuf *cs;
1480 struct radeon_cmdbuf *cs);
1482 struct radeon_cmdbuf *cs);
1486 void si_write_viewport(struct radeon_cmdbuf *cs, int first_vp,
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| D | si_cmd_buffer.c | 38 struct radeon_cmdbuf *cs, in si_write_harvested_raster_configs()
82 struct radeon_cmdbuf *cs) in si_emit_compute()
155 struct radeon_cmdbuf *cs) in si_set_raster_config()
183 struct radeon_cmdbuf *cs) in si_emit_graphics()
596 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, RING_GFX); in cik_create_gfx_config()
655 si_write_viewport(struct radeon_cmdbuf *cs, int first_vp, in si_write_viewport()
714 si_write_scissors(struct radeon_cmdbuf *cs, int first, in si_write_scissors()
928 void si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, in si_cs_emit_write_event_eop()
996 radv_cp_wait_mem(struct radeon_cmdbuf *cs, uint32_t op, uint64_t va, in radv_cp_wait_mem()
1013 si_emit_acquire_mem(struct radeon_cmdbuf *cs, in si_emit_acquire_mem()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_cs.h | 45 struct radeon_cmdbuf *cs, in radeon_cs_memory_below_limit()
121 struct radeon_cmdbuf *cs = ring->cs; in r600_emit_reloc()
131 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
139 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
145 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
153 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
159 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, in radeon_set_context_reg_idx()
170 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
178 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
184 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq()
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| D | r600_viewport.c | 157 struct radeon_cmdbuf *cs, in r600_emit_one_scissor()
188 struct radeon_cmdbuf *cs = rctx->gfx.cs; in r600_emit_guardband()
238 struct radeon_cmdbuf *cs = rctx->gfx.cs; in r600_emit_scissors()
309 struct radeon_cmdbuf *cs = rctx->gfx.cs; in r600_emit_one_viewport()
321 struct radeon_cmdbuf *cs = rctx->gfx.cs; in r600_emit_viewports()
351 struct radeon_cmdbuf *cs = rctx->gfx.cs; in r600_emit_depth_ranges()
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| D | r600_pipe.h | 619 static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs, in r600_emit_command_buffer()
809 struct radeon_cmdbuf *cs,
812 struct radeon_cmdbuf *cs,
985 static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsig… in radeon_compute_set_context_reg_seq()
992 static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_ctl_const_seq()
1000 static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned … in radeon_compute_set_context_reg()
1006 static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned val… in radeon_set_context_reg_flag()
1015 static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_ctl_const()
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| D | evergreen_hw_context.c | 38 struct radeon_cmdbuf *cs = rctx->b.dma.cs; in evergreen_dma_copy_buffer()
88 struct radeon_cmdbuf *cs = rctx->b.gfx.cs; in evergreen_cp_dma_clear_buffer()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_build_pm4.h | 42 static inline void radeon_set_config_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_config_reg_seq()
51 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg()
57 static inline void radeon_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_context_reg_seq()
66 static inline void radeon_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_context_reg()
72 static inline void radeon_set_context_reg_seq_array(struct radeon_cmdbuf *cs, unsigned reg, in radeon_set_context_reg_seq_array()
79 static inline void radeon_set_context_reg_idx(struct radeon_cmdbuf *cs, unsigned reg, unsigned idx, in radeon_set_context_reg_idx()
90 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq()
99 static inline void radeon_set_sh_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_sh_reg()
105 static inline void radeon_set_uconfig_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) in radeon_set_uconfig_reg_seq()
114 static inline void radeon_set_uconfig_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_uconfig_reg()
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| D | si_state_msaa.c | 150 static void si_emit_max_4_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, in si_emit_max_4_sample_locs()
162 static void si_emit_max_16_sample_locs(struct radeon_cmdbuf *cs, uint64_t centroid_priority, in si_emit_max_16_sample_locs()
176 void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples) in si_emit_sample_locations()
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| D | si_dma_cs.c | 30 struct radeon_cmdbuf *cs = sctx->sdma_cs; in si_dma_emit_wait_idle()
41 struct radeon_cmdbuf *cs = sctx->sdma_cs; in si_dma_emit_timestamp()
68 struct radeon_cmdbuf *cs = sctx->sdma_cs; in si_sdma_clear_buffer()
132 struct radeon_cmdbuf *cs = sctx->sdma_cs; in si_sdma_copy_buffer()
289 struct radeon_cmdbuf *cs = ctx->sdma_cs; in si_flush_dma_cs()
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| D | si_pipe.h | 905 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
906 struct radeon_cmdbuf *sdma_cs;
979 struct radeon_cmdbuf *prim_discard_compute_cs;
1367 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1381 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1389 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_saved_cs *saved,
1416 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigned event,
1421 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, uint64_t va, uint32_t ref,
1445 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1838 static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, struct radeon_cmdbuf *cs, in radeon_cs_memory_below_limit()
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| D | si_state_viewport.c | 200 static void si_emit_one_scissor(struct si_context *ctx, struct radeon_cmdbuf *cs, in si_emit_one_scissor()
371 struct radeon_cmdbuf *cs = ctx->gfx_cs; in si_emit_scissors()
478 struct radeon_cmdbuf *cs = ctx->gfx_cs; in si_emit_one_viewport()
490 struct radeon_cmdbuf *cs = ctx->gfx_cs; in si_emit_viewports()
521 struct radeon_cmdbuf *cs = ctx->gfx_cs; in si_emit_depth_ranges()
608 struct radeon_cmdbuf *cs = sctx->gfx_cs; in si_emit_window_rectangles()
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| D | si_state_streamout.c | 216 struct radeon_cmdbuf *cs = sctx->gfx_cs; in gfx10_emit_streamout_begin()
275 struct radeon_cmdbuf *cs = sctx->gfx_cs; in si_flush_vgt_streamout()
302 struct radeon_cmdbuf *cs = sctx->gfx_cs; in si_emit_streamout_begin()
358 struct radeon_cmdbuf *cs = sctx->gfx_cs; in si_emit_streamout_end()
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| /external/mesa3d/src/amd/vulkan/winsys/null/ |
| D | radv_null_cs.c | 32 struct radeon_cmdbuf base;
37 radv_null_cs(struct radeon_cmdbuf *base) in radv_null_cs()
61 static struct radeon_cmdbuf *
81 static VkResult radv_null_cs_finalize(struct radeon_cmdbuf *_cs) in radv_null_cs_finalize()
86 static void radv_null_cs_destroy(struct radeon_cmdbuf *rcs) in radv_null_cs_destroy()
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| /external/mesa3d/src/amd/common/ |
| D | ac_shadowed_regs.h | 31 struct radeon_cmdbuf;
50 typedef void (*set_context_reg_seq_array_fn)(struct radeon_cmdbuf *cs, unsigned reg, unsigned num,
56 void ac_emulate_clear_state(const struct radeon_info *info, struct radeon_cmdbuf *cs,
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| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| D | radv_amdgpu_cs.c | 45 struct radeon_cmdbuf base;
72 struct radeon_cmdbuf *old_cs_buffers;
77 radv_amdgpu_cs(struct radeon_cmdbuf *base) in radv_amdgpu_cs()
278 static void radv_amdgpu_cs_destroy(struct radeon_cmdbuf *rcs) in radv_amdgpu_cs_destroy()
291 struct radeon_cmdbuf *rcs = &cs->old_cs_buffers[i]; in radv_amdgpu_cs_destroy()
312 static struct radeon_cmdbuf *
365 static void radv_amdgpu_cs_grow(struct radeon_cmdbuf *_cs, size_t min_size) in radv_amdgpu_cs_grow()
385 struct radeon_cmdbuf *old_cs_buffers = in radv_amdgpu_cs_grow()
492 static VkResult radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs) in radv_amdgpu_cs_finalize()
508 static void radv_amdgpu_cs_reset(struct radeon_cmdbuf *_cs) in radv_amdgpu_cs_reset()
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| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| D | radeon_drm_cs.h | 73 struct radeon_cmdbuf base;
100 radeon_drm_cs(struct radeon_cmdbuf *base) in radeon_drm_cs()
139 void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs);
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| D | radeon_drm_cs.c | 69 static struct pipe_fence_handle *radeon_cs_create_fence(struct radeon_cmdbuf *rcs);
165 static struct radeon_cmdbuf *
350 static unsigned radeon_drm_cs_add_buffer(struct radeon_cmdbuf *rcs, in radeon_drm_cs_add_buffer()
397 static int radeon_drm_cs_lookup_buffer(struct radeon_cmdbuf *rcs, in radeon_drm_cs_lookup_buffer()
405 static bool radeon_drm_cs_validate(struct radeon_cmdbuf *rcs) in radeon_drm_cs_validate()
444 static bool radeon_drm_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw, in radeon_drm_cs_check_space()
451 static unsigned radeon_drm_cs_get_buffer_list(struct radeon_cmdbuf *rcs, in radeon_drm_cs_get_buffer_list()
502 void radeon_drm_cs_sync_flush(struct radeon_cmdbuf *rcs) in radeon_drm_cs_sync_flush()
563 static int radeon_drm_cs_flush(struct radeon_cmdbuf *rcs, in radeon_drm_cs_flush()
723 static void radeon_drm_cs_destroy(struct radeon_cmdbuf *rcs) in radeon_drm_cs_destroy()
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| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| D | amdgpu_cs.h | 66 struct radeon_cmdbuf base;
213 amdgpu_ib(struct radeon_cmdbuf *base) in amdgpu_ib()
219 amdgpu_cs(struct radeon_cmdbuf *base) in amdgpu_cs()
283 void amdgpu_cs_sync_flush(struct radeon_cmdbuf *rcs);
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| D | amdgpu_cs.c | 257 amdgpu_cs_get_next_fence(struct radeon_cmdbuf *rcs) in amdgpu_cs_get_next_fence()
622 static unsigned amdgpu_cs_add_buffer(struct radeon_cmdbuf *rcs, in amdgpu_cs_add_buffer()
949 static struct radeon_cmdbuf *
1007 static struct radeon_cmdbuf *
1008 amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf *ib, in amdgpu_cs_add_parallel_compute_ib()
1035 amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_ib, in amdgpu_cs_setup_preemption()
1088 static bool amdgpu_cs_validate(struct radeon_cmdbuf *rcs) in amdgpu_cs_validate()
1093 static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw, in amdgpu_cs_check_space()
1188 static unsigned amdgpu_cs_get_buffer_list(struct radeon_cmdbuf *rcs, in amdgpu_cs_get_buffer_list()
1246 static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rws, in amdgpu_cs_add_fence_dependency()
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| /external/mesa3d/src/amd/vulkan/layers/ |
| D | radv_sqtt_layer.c | 359 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_write_begin_general_api_marker()
372 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_write_end_general_api_marker()
389 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_write_event_marker()
418 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_write_event_with_dims_marker()
438 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_describe_begin_cmd_buffer()
463 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_describe_end_cmd_buffer()
515 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_describe_barrier_end_delayed()
572 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_describe_barrier_start()
598 struct radeon_cmdbuf *cs = cmd_buffer->cs; in radv_describe_layout_transition()
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