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Searched refs:radeon_emit (Results 1 – 25 of 48) sorted by relevance

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/external/mesa3d/src/amd/vulkan/
Dradv_cs.h48 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
49 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
55 radeon_emit(cs, value); in radeon_set_config_reg()
63 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
64 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
70 radeon_emit(cs, value); in radeon_set_context_reg()
80 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
81 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
82 radeon_emit(cs, value); in radeon_set_context_reg_idx()
91 radeon_emit(cs, PKT3(PKT3_CONTEXT_REG_RMW, 2, 0)); in radeon_set_context_reg_rmw()
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Dsi_cmd_buffer.c85 radeon_emit(cs, 0); in si_emit_compute()
86 radeon_emit(cs, 0); in si_emit_compute()
87 radeon_emit(cs, 0); in si_emit_compute()
92 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
93 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_compute()
99 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | in si_emit_compute()
101 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | in si_emit_compute()
108 radeon_emit(cs, bc_va >> 8); in si_emit_compute()
109 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); in si_emit_compute()
190 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); in si_emit_graphics()
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Dradv_sqtt.c205 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_start()
206 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_START) | EVENT_INDEX(0)); in radv_emit_thread_trace_start()
257 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in radv_copy_thread_trace_info_regs()
258 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) | in radv_copy_thread_trace_info_regs()
261 radeon_emit(cs, thread_trace_info_regs[i] >> 2); in radv_copy_thread_trace_info_regs()
262 radeon_emit(cs, 0); /* unused */ in radv_copy_thread_trace_info_regs()
263 radeon_emit(cs, (info_va + i * 4)); in radv_copy_thread_trace_info_regs()
264 radeon_emit(cs, (info_va + i * 4) >> 32); in radv_copy_thread_trace_info_regs()
283 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_emit_thread_trace_stop()
284 radeon_emit(cs, EVENT_TYPE(V_028A90_THREAD_TRACE_STOP) | EVENT_INDEX(0)); in radv_emit_thread_trace_stop()
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Dradv_cmd_buffer.c570 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0)); in radv_emit_write_data_packet()
571 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | in radv_emit_write_data_packet()
574 radeon_emit(cs, va); in radv_emit_write_data_packet()
575 radeon_emit(cs, va >> 32); in radv_emit_write_data_packet()
595 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in radv_cmd_buffer_trace_emit()
596 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id)); in radv_cmd_buffer_trace_emit()
604 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cmd_buffer_after_draw()
605 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0)); in radv_cmd_buffer_after_draw()
921 radeon_emit(cs, centroid_priority); in radv_emit_sample_locations()
922 radeon_emit(cs, centroid_priority >> 32); in radv_emit_sample_locations()
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Dradv_query.c1653 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_begin_query()
1654 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); in emit_begin_query()
1655 radeon_emit(cs, va); in emit_begin_query()
1656 radeon_emit(cs, va >> 32); in emit_begin_query()
1667 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in emit_begin_query()
1668 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); in emit_begin_query()
1669 radeon_emit(cs, va); in emit_begin_query()
1670 radeon_emit(cs, va >> 32); in emit_begin_query()
1682 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); in emit_begin_query()
1683 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_GDS) | in emit_begin_query()
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/external/mesa3d/src/gallium/drivers/r600/
Dcayman_msaa.c168 radeon_emit(cs, cm_sample_locs_8x[0]); in cayman_emit_msaa_sample_locs()
169 radeon_emit(cs, cm_sample_locs_8x[4]); in cayman_emit_msaa_sample_locs()
170 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
171 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
172 radeon_emit(cs, cm_sample_locs_8x[1]); in cayman_emit_msaa_sample_locs()
173 radeon_emit(cs, cm_sample_locs_8x[5]); in cayman_emit_msaa_sample_locs()
174 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
175 radeon_emit(cs, 0); in cayman_emit_msaa_sample_locs()
176 radeon_emit(cs, cm_sample_locs_8x[2]); in cayman_emit_msaa_sample_locs()
177 radeon_emit(cs, cm_sample_locs_8x[6]); in cayman_emit_msaa_sample_locs()
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Dr600_streamout.c169 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_vgt_streamout()
170 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); in r600_flush_vgt_streamout()
172 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in r600_flush_vgt_streamout()
173 radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ in r600_flush_vgt_streamout()
174 radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ in r600_flush_vgt_streamout()
175 radeon_emit(cs, 0); in r600_flush_vgt_streamout()
176 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */ in r600_flush_vgt_streamout()
177 radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */ in r600_flush_vgt_streamout()
178 radeon_emit(cs, 4); /* poll interval */ in r600_flush_vgt_streamout()
201 radeon_emit(cs, (t[i]->b.buffer_offset + in r600_emit_streamout_begin()
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Dr600_hw_context.c125 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
126 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in r600_flush_emit()
130 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
131 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in r600_flush_emit()
144 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
145 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in r600_flush_emit()
150 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
151 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in r600_flush_emit()
164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in r600_flush_emit()
165 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); in r600_flush_emit()
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Dr600_cs.h126 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); in r600_emit_reloc()
127 radeon_emit(cs, reloc); in r600_emit_reloc()
135 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
136 radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
142 radeon_emit(cs, value); in radeon_set_config_reg()
149 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
150 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
156 radeon_emit(cs, value); in radeon_set_context_reg()
165 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
166 radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
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Devergreen_hw_context.c69 radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, csize)); in evergreen_dma_copy_buffer()
70 radeon_emit(cs, dst_offset & 0xffffffff); in evergreen_dma_copy_buffer()
71 radeon_emit(cs, src_offset & 0xffffffff); in evergreen_dma_copy_buffer()
72 radeon_emit(cs, (dst_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
73 radeon_emit(cs, (src_offset >> 32UL) & 0xff); in evergreen_dma_copy_buffer()
129 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in evergreen_cp_dma_clear_buffer()
130 radeon_emit(cs, clear_value); /* DATA [31:0] */ in evergreen_cp_dma_clear_buffer()
131 radeon_emit(cs, sync | PKT3_CP_DMA_SRC_SEL(2)); /* CP_SYNC [31] | SRC_SEL[30:29] */ in evergreen_cp_dma_clear_buffer()
132 radeon_emit(cs, offset); /* DST_ADDR_LO [31:0] */ in evergreen_cp_dma_clear_buffer()
133 radeon_emit(cs, (offset >> 32) & 0xff); /* DST_ADDR_HI [7:0] */ in evergreen_cp_dma_clear_buffer()
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Devergreen_state.c983 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs)); in evergreen_emit_config_state()
984 radeon_emit(cs, 0); in evergreen_emit_config_state()
985 radeon_emit(cs, 0); in evergreen_emit_config_state()
987 radeon_emit(cs, a->sq_gpr_resource_mgmt_1); in evergreen_emit_config_state()
988 radeon_emit(cs, a->sq_gpr_resource_mgmt_2); in evergreen_emit_config_state()
989 radeon_emit(cs, a->sq_gpr_resource_mgmt_3); in evergreen_emit_config_state()
1687 radeon_emit(cs, S_028C00_LAST_PIXEL(1) | in evergreen_emit_msaa_state()
1689 radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | in evergreen_emit_msaa_state()
1697 radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ in evergreen_emit_msaa_state()
1698 radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ in evergreen_emit_msaa_state()
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Devergreen_compute.c636 radeon_emit(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */ in evergreen_emit_dispatch()
637 radeon_emit(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */ in evergreen_emit_dispatch()
638 radeon_emit(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */ in evergreen_emit_dispatch()
644 radeon_emit(cs, info->block[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */ in evergreen_emit_dispatch()
645 radeon_emit(cs, info->block[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */ in evergreen_emit_dispatch()
646 radeon_emit(cs, info->block[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */ in evergreen_emit_dispatch()
660 radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, render_cond_bit)); in evergreen_emit_dispatch()
661 radeon_emit(cs, indirect_grid[0]); in evergreen_emit_dispatch()
662 radeon_emit(cs, indirect_grid[1]); in evergreen_emit_dispatch()
663 radeon_emit(cs, indirect_grid[2]); in evergreen_emit_dispatch()
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Dr600_state.c276 radeon_emit(cs, fui(offset_scale)); in r600_emit_polygon_offset()
277 radeon_emit(cs, fui(offset_units)); in r600_emit_polygon_offset()
278 radeon_emit(cs, fui(offset_scale)); in r600_emit_polygon_offset()
279 radeon_emit(cs, fui(offset_units)); in r600_emit_polygon_offset()
1303 radeon_emit(cs, sample_locs_8x[0]); /* R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0 */ in r600_emit_msaa_state()
1304 radeon_emit(cs, sample_locs_8x[1]); /* R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1 */ in r600_emit_msaa_state()
1312 radeon_emit(cs, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ in r600_emit_msaa_state()
1313 radeon_emit(cs, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ in r600_emit_msaa_state()
1318 radeon_emit(cs, sample_locs_2x[0]); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ in r600_emit_msaa_state()
1319 radeon_emit(cs, sample_locs_2x[1]); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX */ in r600_emit_msaa_state()
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Dr600_viewport.c175 radeon_emit(cs, S_028250_TL_X(final.minx) | in r600_emit_one_scissor()
178 radeon_emit(cs, S_028254_BR_X(final.maxx) | in r600_emit_one_scissor()
230 radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */ in r600_emit_guardband()
231 radeon_emit(cs, fui(1.0)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */ in r600_emit_guardband()
232 radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */ in r600_emit_guardband()
233 radeon_emit(cs, fui(1.0)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */ in r600_emit_guardband()
311 radeon_emit(cs, fui(state->scale[0])); in r600_emit_one_viewport()
312 radeon_emit(cs, fui(state->translate[0])); in r600_emit_one_viewport()
313 radeon_emit(cs, fui(state->scale[1])); in r600_emit_one_viewport()
314 radeon_emit(cs, fui(state->translate[1])); in r600_emit_one_viewport()
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/external/mesa3d/src/gallium/drivers/radeonsi/
Dcik_sdma.c114 radeon_emit( in si_sdma_v4_copy_texture()
118 radeon_emit(cs, src_address); in si_sdma_v4_copy_texture()
119 radeon_emit(cs, src_address >> 32); in si_sdma_v4_copy_texture()
120 radeon_emit(cs, srcx | (srcy << 16)); in si_sdma_v4_copy_texture()
121 radeon_emit(cs, srcz | ((src_pitch - 1) << 13)); in si_sdma_v4_copy_texture()
122 radeon_emit(cs, src_slice_pitch - 1); in si_sdma_v4_copy_texture()
123 radeon_emit(cs, dst_address); in si_sdma_v4_copy_texture()
124 radeon_emit(cs, dst_address >> 32); in si_sdma_v4_copy_texture()
125 radeon_emit(cs, dstx | (dsty << 16)); in si_sdma_v4_copy_texture()
126 radeon_emit(cs, dstz | ((dst_pitch - 1) << 13)); in si_sdma_v4_copy_texture()
[all …]
Dsi_build_pm4.h47 radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); in radeon_set_config_reg_seq()
48 radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2); in radeon_set_config_reg_seq()
54 radeon_emit(cs, value); in radeon_set_config_reg()
62 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); in radeon_set_context_reg_seq()
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
69 radeon_emit(cs, value); in radeon_set_context_reg()
85 radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); in radeon_set_context_reg_idx()
86 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
87 radeon_emit(cs, value); in radeon_set_context_reg_idx()
95 radeon_emit(cs, PKT3(PKT3_SET_SH_REG, num, 0)); in radeon_set_sh_reg_seq()
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Dsi_state_streamout.c240 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); in gfx10_emit_streamout_begin()
241 radeon_emit(cs, S_411_SRC_SEL(append ? V_411_SRC_ADDR_TC_L2 : V_411_DATA) | in gfx10_emit_streamout_begin()
243 radeon_emit(cs, va); in gfx10_emit_streamout_begin()
244 radeon_emit(cs, va >> 32); in gfx10_emit_streamout_begin()
245 radeon_emit(cs, 4 * i); /* destination in GDS */ in gfx10_emit_streamout_begin()
246 radeon_emit(cs, 0); in gfx10_emit_streamout_begin()
247 radeon_emit(cs, S_414_BYTE_COUNT_GFX9(4) | S_414_DISABLE_WR_CONFIRM_GFX9(i != last_target)); in gfx10_emit_streamout_begin()
287 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_flush_vgt_streamout()
288 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); in si_flush_vgt_streamout()
290 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); in si_flush_vgt_streamout()
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Dsi_dma_cs.c34 radeon_emit(cs, 0x00000000); /* NOP */ in si_dma_emit_wait_idle()
36 radeon_emit(cs, 0xf0000000); /* NOP */ in si_dma_emit_wait_idle()
59 radeon_emit( in si_dma_emit_timestamp()
61 radeon_emit(cs, va); in si_dma_emit_timestamp()
62 radeon_emit(cs, va >> 32); in si_dma_emit_timestamp()
97 radeon_emit(cs, SI_DMA_PACKET(SI_DMA_PACKET_CONSTANT_FILL, 0, csize / 4)); in si_sdma_clear_buffer()
98 radeon_emit(cs, offset); in si_sdma_clear_buffer()
99 radeon_emit(cs, clear_value); in si_sdma_clear_buffer()
100 radeon_emit(cs, (offset >> 32) << 16); in si_sdma_clear_buffer()
117 radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_PACKET_CONSTANT_FILL, 0, 0x8000 /* dword copy */)); in si_sdma_clear_buffer()
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Dsi_state_draw.c262 radeon_emit(cs, offchip_layout); in si_emit_derived_tess_state()
263 radeon_emit(cs, tcs_out_offsets); in si_emit_derived_tess_state()
264 radeon_emit(cs, tcs_out_layout); in si_emit_derived_tess_state()
276 radeon_emit(cs, ls_current->config.rsrc1); in si_emit_derived_tess_state()
277 radeon_emit(cs, ls_rsrc2); in si_emit_derived_tess_state()
282 radeon_emit(cs, offchip_layout); in si_emit_derived_tess_state()
283 radeon_emit(cs, tcs_out_offsets); in si_emit_derived_tess_state()
284 radeon_emit(cs, tcs_out_layout); in si_emit_derived_tess_state()
285 radeon_emit(cs, tcs_in_layout); in si_emit_derived_tess_state()
290 radeon_emit(cs, offchip_layout); in si_emit_derived_tess_state()
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Dsi_fence.c94 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in si_cp_release_mem()
95 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); in si_cp_release_mem()
96 radeon_emit(cs, scratch->gpu_address); in si_cp_release_mem()
97 radeon_emit(cs, scratch->gpu_address >> 32); in si_cp_release_mem()
103 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, ctx->chip_class >= GFX9 ? 6 : 5, 0)); in si_cp_release_mem()
104 radeon_emit(cs, op); in si_cp_release_mem()
105 radeon_emit(cs, sel); in si_cp_release_mem()
106 radeon_emit(cs, va); /* address lo */ in si_cp_release_mem()
107 radeon_emit(cs, va >> 32); /* address hi */ in si_cp_release_mem()
108 radeon_emit(cs, new_fence); /* immediate data lo */ in si_cp_release_mem()
[all …]
Dsi_compute.c355 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_initial_compute_regs()
356 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_initial_compute_regs()
375 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_initial_compute_regs()
376 radeon_emit(cs, S_00B858_SH0_CU_EN(0xffff) | S_00B858_SH1_CU_EN(0xffff)); in si_emit_initial_compute_regs()
386 radeon_emit(cs, bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */ in si_emit_initial_compute_regs()
387 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */ in si_emit_initial_compute_regs()
509 radeon_emit(cs, shader_va >> 8); in si_switch_compute_shader()
510 radeon_emit(cs, S_00B834_DATA(shader_va >> 40)); in si_switch_compute_shader()
513 radeon_emit(cs, config->rsrc1); in si_switch_compute_shader()
514 radeon_emit(cs, config->rsrc2); in si_switch_compute_shader()
[all …]
Dsi_cp_dma.c106 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, 0)); in si_emit_cp_dma()
107 radeon_emit(cs, header); in si_emit_cp_dma()
108 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
109 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */ in si_emit_cp_dma()
110 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */ in si_emit_cp_dma()
111 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */ in si_emit_cp_dma()
112 radeon_emit(cs, command); in si_emit_cp_dma()
116 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); in si_emit_cp_dma()
117 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */ in si_emit_cp_dma()
118 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */ in si_emit_cp_dma()
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Dsi_compute_prim_discard.c1088 radeon_emit(gfx_cs, PKT3(PKT3_NOP, 0, 0)); in si_prepare_prim_discard_or_split_draw()
1089 radeon_emit(gfx_cs, 0); in si_prepare_prim_discard_or_split_draw()
1188 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in si_dispatch_prim_discard_cs_and_draw()
1189 radeon_emit(cs, 0); /* CP_COHER_CNTL */ in si_dispatch_prim_discard_cs_and_draw()
1190 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in si_dispatch_prim_discard_cs_and_draw()
1191 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */ in si_dispatch_prim_discard_cs_and_draw()
1192 radeon_emit(cs, 0); /* CP_COHER_BASE */ in si_dispatch_prim_discard_cs_and_draw()
1193 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ in si_dispatch_prim_discard_cs_and_draw()
1194 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in si_dispatch_prim_discard_cs_and_draw()
1195 radeon_emit(cs, /* GCR_CNTL */ in si_dispatch_prim_discard_cs_and_draw()
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Dsi_perfcounter.c734 radeon_emit(cs, shaders & 0x7f); in si_pc_emit_shaders()
735 radeon_emit(cs, 0xffffffff); in si_pc_emit_shaders()
760 radeon_emit(cs, 0); in si_pc_emit_select()
762 radeon_emit(cs, selectors[idx] | regs->select_or); in si_pc_emit_select()
770 radeon_emit(cs, 0); in si_pc_emit_select()
774 radeon_emit(cs, selectors[idx] | regs->select_or); in si_pc_emit_select()
783 radeon_emit(cs, 0); in si_pc_emit_select()
785 radeon_emit(cs, selectors[idx] | regs->select_or); in si_pc_emit_select()
791 radeon_emit(cs, 0); in si_pc_emit_select()
810 radeon_emit(cs, 0); in si_pc_emit_select()
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Dsi_state_viewport.c220 radeon_emit(cs, S_028250_TL_X(1) | S_028250_TL_Y(1) | S_028250_WINDOW_OFFSET_DISABLE(1)); in si_emit_one_scissor()
221 radeon_emit(cs, S_028254_BR_X(1) | S_028254_BR_Y(1)); in si_emit_one_scissor()
225 radeon_emit(cs, S_028250_TL_X(final.minx) | S_028250_TL_Y(final.miny) | in si_emit_one_scissor()
227 radeon_emit(cs, S_028254_BR_X(final.maxx) | S_028254_BR_Y(final.maxy)); in si_emit_one_scissor()
480 radeon_emit(cs, fui(state->scale[0])); in si_emit_one_viewport()
481 radeon_emit(cs, fui(state->translate[0])); in si_emit_one_viewport()
482 radeon_emit(cs, fui(state->scale[1])); in si_emit_one_viewport()
483 radeon_emit(cs, fui(state->translate[1])); in si_emit_one_viewport()
484 radeon_emit(cs, fui(state->scale[2])); in si_emit_one_viewport()
485 radeon_emit(cs, fui(state->translate[2])); in si_emit_one_viewport()
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