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/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1792 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1793 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1798 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1799 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
1803 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
1804 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
1805 regclass:$dst4),
1812 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
1813 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1815 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
[all …]
DNVPTXVector.td239 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
241 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a, regclass:$b),
243 [(set regclass:$dst, (OpNode regclass:$a, regclass:$b))],
253 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
255 NVPTXVecInst<(outs regclass:$dst), (ins regclass:$a),
257 [(set regclass:$dst, (OpNode regclass:$a))], sInst>;
493 multiclass VMADV2Only<string asmstr, NVPTXRegClass regclass, NVPTXInst sop=NOP,
495 def V2 : NVPTXVecInst<(outs regclass:$dst),
496 (ins regclass:$a, regclass:$b, regclass:$c),
498 [(set regclass:$dst, (add
[all …]
DNVPTXIntrinsics.td69 multiclass SHFL<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
75 (outs regclass:$dst),
76 (ins regclass:$src, Int32Regs:$offset, Int32Regs:$mask),
78 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, Int32Regs:$mask))]>;
81 (outs regclass:$dst),
82 (ins regclass:$src, i32imm:$offset, Int32Regs:$mask),
84 [(set regclass:$dst, (IntOp regclass:$src, imm:$offset, Int32Regs:$mask))]>;
87 (outs regclass:$dst),
88 (ins regclass:$src, Int32Regs:$offset, i32imm:$mask),
90 [(set regclass:$dst, (IntOp regclass:$src, Int32Regs:$offset, imm:$mask))]>;
[all …]
/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1992 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1993 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1997 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1998 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
2002 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
2003 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
2004 regclass:$dst4),
2011 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
2012 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
2014 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
[all …]
DNVPTXIntrinsics.td178 foreach regclass = ["i32", "f32"] in {
183 def : SHFL_INSTR<sync, mode, regclass, return_pred,
195 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
196 def : NVPTXInst<(outs regclass:$dest), (ins Int1Regs:$pred),
198 [(set regclass:$dest, (IntOp Int1Regs:$pred))]>,
208 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
209 def i : NVPTXInst<(outs regclass:$dest), (ins i32imm:$mask, Int1Regs:$pred),
211 [(set regclass:$dest, (IntOp imm:$mask, Int1Regs:$pred))]>,
213 def r : NVPTXInst<(outs regclass:$dest), (ins Int32Regs:$mask, Int1Regs:$pred),
215 [(set regclass:$dest, (IntOp Int32Regs:$mask, Int1Regs:$pred))]>,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1992 class LoadParamMemInst<NVPTXRegClass regclass, string opstr> :
1993 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
1997 class LoadParamV2MemInst<NVPTXRegClass regclass, string opstr> :
1998 NVPTXInst<(outs regclass:$dst, regclass:$dst2), (ins i32imm:$b),
2002 class LoadParamV4MemInst<NVPTXRegClass regclass, string opstr> :
2003 NVPTXInst<(outs regclass:$dst, regclass:$dst2, regclass:$dst3,
2004 regclass:$dst4),
2011 class LoadParamRegInst<NVPTXRegClass regclass, string opstr> :
2012 NVPTXInst<(outs regclass:$dst), (ins i32imm:$b),
2014 [(set regclass:$dst, (LoadParam (i32 0), (i32 imm:$b)))]>;
[all …]
DNVPTXIntrinsics.td178 foreach regclass = ["i32", "f32"] in {
183 def : SHFL_INSTR<sync, mode, regclass, return_pred,
195 multiclass VOTE<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
196 def : NVPTXInst<(outs regclass:$dest), (ins Int1Regs:$pred),
198 [(set regclass:$dest, (IntOp Int1Regs:$pred))]>,
208 multiclass VOTE_SYNC<NVPTXRegClass regclass, string mode, Intrinsic IntOp> {
209 def i : NVPTXInst<(outs regclass:$dest), (ins i32imm:$mask, Int1Regs:$pred),
211 [(set regclass:$dest, (IntOp imm:$mask, Int1Regs:$pred))]>,
213 def r : NVPTXInst<(outs regclass:$dest), (ins Int32Regs:$mask, Int1Regs:$pred),
215 [(set regclass:$dest, (IntOp Int32Regs:$mask, Int1Regs:$pred))]>,
[all …]
/external/llvm-project/libunwind/src/
DUnwind-EHABI.cpp760 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Set() argument
765 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Set()
769 switch (regclass) { in _Unwind_VRS_Set()
819 _Unwind_VRS_RegClass regclass, uint32_t regno, in _Unwind_VRS_Get_Internal() argument
823 switch (regclass) { in _Unwind_VRS_Get_Internal()
872 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Get() argument
876 _Unwind_VRS_Get_Internal(context, regclass, regno, representation, in _Unwind_VRS_Get()
880 static_cast<void *>(context), regclass, regno, in _Unwind_VRS_Get()
887 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass, in _Unwind_VRS_Pop() argument
892 static_cast<void *>(context), regclass, discriminator, in _Unwind_VRS_Pop()
[all …]
/external/llvm-project/libunwind/include/
Dunwind.h200 _Unwind_VRS_Get(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
205 _Unwind_VRS_Set(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
210 _Unwind_VRS_Pop(_Unwind_Context *context, _Unwind_VRS_RegClass regclass,
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvariable_elem_vec_extracts.ll100 ; FIXME: the instruction below is a redundant regclass copy, to be removed
106 ; FIXME: the instruction below is a redundant regclass copy, to be removed
112 ; FIXME: the instruction below is a redundant regclass copy, to be removed
/external/llvm/test/CodeGen/PowerPC/
Dvariable_elem_vec_extracts.ll100 ; FIXME: the instruction below is a redundant regclass copy, to be removed
106 ; FIXME: the instruction below is a redundant regclass copy, to be removed
112 ; FIXME: the instruction below is a redundant regclass copy, to be removed
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrCDE.td471 class CDE_VCX_RegisterOperandsTemplate<RegisterClass regclass>
473 let Rd = (outs regclass:$Vd);
474 let Rd_src = (ins regclass:$Vd_src);
475 let Rn = (ins regclass:$Vn);
476 let Rm = (ins regclass:$Vm);
479 class CDE_VCXQ_RegisterOperandsTemplate<RegisterClass regclass>
481 let Rd = (outs regclass:$Qd);
482 let Rd_src = (ins regclass:$Qd_src);
483 let Rn = (ins regclass:$Qn);
484 let Rm = (ins regclass:$Qm);
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dlocalizer.mir90 ; The newly created reg should be on the same regbank/regclass as its origin.
117 ; The newly created reg should be on the same regbank/regclass as its origin.
148 ; The newly created reg should be on the same regbank/regclass as its origin.
184 ; The newly created reg should be on the same regbank/regclass as its origin.
220 ; The newly created reg should be on the same regbank/regclass as its origin.
256 ; The newly created reg should be on the same regbank/regclass as its origin.
293 ; The newly created reg should be on the same regbank/regclass as its origin.
330 ; The newly created reg should be on the same regbank/regclass as its origin.
/external/llvm/test/CodeGen/X86/
Dcoalescer-subreg.ll2 ; This used to crash when coalescing a regclass like GR16 which did not support
Dh-registers-0.ll14 ; See FIXME: on regclass GR8.
/external/llvm-project/llvm/test/CodeGen/X86/
Dcoalescer-subreg.ll2 ; This used to crash when coalescing a regclass like GR16 which did not support
Dh-registers-0.ll38 ; See FIXME: on regclass GR8.
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVPseudos.td22 class LMULInfo<int lmul, VReg regclass, string mx> {
24 VReg vrclass = regclass;
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dearly-ifcvt-regclass-mismatch.mir116 ; some operands to the PHI have the fpr64 regclass.
/external/mesa3d/docs/relnotes/
D20.0.3.rst145 - aco: fix boolean undef regclass
/external/llvm/include/llvm/Target/
DTargetOpcodes.def81 // pair. Once it has been lowered to a MachineInstr, the regclass operand
DTarget.td553 /// type that it doesn't know, and resolves the actual regclass to use by using
664 class RegisterOperand<RegisterClass regclass, string pm = "printOperand">
667 RegisterClass RegClass = regclass;
849 let InOperandList = (ins unknown:$src, i32imm:$regclass);
/external/llvm/test/CodeGen/ARM/
Dvldlane.ll503 ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because
504 ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td550 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
565 RegisterClass RegClass = regclass;
672 // both a regclass and EFLAGS as a result.
681 // both a regclass and EFLAGS as a result, and has EFLAGS as input.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td539 class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
554 RegisterClass RegClass = regclass;
657 // both a regclass and EFLAGS as a result.
665 // both a regclass and EFLAGS as a result, and has EFLAGS as input.

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