s512 (reference) in projects: external - OpenGrok search results

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Searched refs:s512 (Results 1 – 24 of 24) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	inst-select-extract.mir	`45 %0:sgpr(s512) = G_IMPLICIT_DEF 46 %1:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 0 47 %2:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 32 48 %3:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 64 49 %4:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 96 50 %5:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 128 51 %6:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 160 52 %7:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 192 53 %8:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 224 54 %9:sgpr(s32) = G_EXTRACT %0:sgpr(s512), 256 [all …]`
D	inst-select-insert.mir	33 %0:sgpr(s512) = G_IMPLICIT_DEF 35 %2:sgpr(s512) = G_INSERT %0:sgpr, %1:sgpr(s32), 0 36 %3:sgpr(s512) = G_INSERT %2:sgpr, %1:sgpr(s32), 32 37 %4:sgpr(s512) = G_INSERT %3:sgpr, %1:sgpr(s32), 64 38 %5:sgpr(s512) = G_INSERT %4:sgpr, %1:sgpr(s32), 96 39 %6:sgpr(s512) = G_INSERT %5:sgpr, %1:sgpr(s32), 128 40 %7:sgpr(s512) = G_INSERT %6:sgpr, %1:sgpr(s32), 160 41 %8:sgpr(s512) = G_INSERT %7:sgpr, %1:sgpr(s32), 192 42 %9:sgpr(s512) = G_INSERT %8:sgpr, %1:sgpr(s32), 224 43 %10:sgpr(s512) = G_INSERT %9:sgpr, %1:sgpr(s32), 256 [all …]
D	inst-select-unmerge-values.mir	`254 ; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](s1024) 255 …3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY [[UV]](s512) 256 …0_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31 = COPY [[UV1]](s512) 265 %1:sgpr(s512), %2:sgpr(s512) = G_UNMERGE_VALUES %0`
D	legalize-freeze.mir	179 …; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vg… 180 ; CHECK: [[TRUNC:%[0-9]+]]:_(s448) = G_TRUNC [[COPY]](s512) 184 …; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[UV]](s64), [[UV1]](s64), [[UV2]](s64), [[UV3]](… 185 …3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512) 186 …%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr1… 189 %3:_(s512) = G_ANYEXT %2 199 …; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vg… 200 ; CHECK: [[FREEZE:%[0-9]+]]:_(s512) = G_FREEZE [[COPY]] 201 …pr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[FREEZE]](s512) 202 …%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr1… [all …]
D	regbankselect-freeze.mir	265 …; CHECK: [[COPY:%[0-9]+]]:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8… 266 ; CHECK: [[FREEZE:%[0-9]+]]:vgpr(s512) = G_FREEZE [[COPY]] 267 …pr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[FREEZE]](s512) 268 …%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr1… 269 %1:_(s512) = G_FREEZE %0 270 …vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1(s512)
D	legalize-unmerge-values.mir	950 …; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vg… 951 ; CHECK: [[UV:%[0-9]+]]:_(s256), [[UV1:%[0-9]+]]:_(s256) = G_UNMERGE_VALUES [[COPY]](s512) 954 …%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr… 987 ; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](s1024) 988 …3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512) 989 …0_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31 = COPY [[UV1]](s512) 991 %1:_(s512), %2:_(s512) = G_UNMERGE_VALUES %0 1004 …; CHECK: [[COPY:%[0-9]+]]:_(<2 x s512>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vg… 1005 ; CHECK: [[UV:%[0-9]+]]:_(s512), [[UV1:%[0-9]+]]:_(s512) = G_UNMERGE_VALUES [[COPY]](<2 x s512>) 1006 …3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[UV]](s512) [all …]
D	inst-select-merge-values.mir	`404 %4:sgpr(s512) = G_MERGE_VALUES %0, %1 438 %8:sgpr(s512) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6, %7 472 %8:vgpr(s512) = G_MERGE_VALUES %0, %1, %2, %3, %4, %5, %6, %7 563 …%0:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sg… 564 …%1:sgpr(s512) = COPY $sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26…`
D	legalize-anyext.mir	`399 …; CHECK: [[MV1:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[MV]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF… 400 ; CHECK: S_ENDPGM 0, implicit [[MV1]](s512) 402 %1:_(s512) = G_ANYEXT %0 500 …; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]… 501 ; CHECK: S_ENDPGM 0, implicit [[MV]](s512) 503 %1:_(s512) = G_ANYEXT %0`
D	legalize-sext-inreg.mir	540 …; GFX9: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgp… 541 ; GFX9: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512) 545 …; GFX9: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64),… 546 …3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512) 548 …; GFX8: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgp… 549 ; GFX8: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512) 553 …; GFX8: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[SEXT_INREG]](s64), [[ASHR]](s64), [[ASHR]](s64),… 554 …3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512) 556 …; GFX6: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgp… 557 ; GFX6: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY]](s512) [all …]
D	legalize-zext.mir	`440 …; CHECK: [[MV1:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[MV]](s64), [[C1]](s64), [[C1]](s64), [[C1]](s6… 441 ; CHECK: S_ENDPGM 0, implicit [[MV1]](s512) 443 %1:_(s512) = G_ZEXT %0 541 …; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s64), [[C]](s64), [[C]](s64), [[C]](s64)… 542 ; CHECK: S_ENDPGM 0, implicit [[MV]](s512) 544 %1:_(s512) = G_ZEXT %0`
D	legalize-sext.mir	`427 …; CHECK: [[MV2:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV1]](s64), [[MV1]]… 428 ; CHECK: S_ENDPGM 0, implicit [[MV2]](s512) 430 %1:_(s512) = G_SEXT %0 535 …; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s64), [[ASHR]](s64), [[ASHR]](s64), [[AS… 536 ; CHECK: S_ENDPGM 0, implicit [[MV]](s512) 538 %1:_(s512) = G_SEXT %0`
D	inst-select-trunc.mir	`185 …%0:sgpr(s512) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sg… 370 …%0:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vg…`
D	inst-select-freeze.mir	`329 …%0:vgpr(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vg… 330 %1:vgpr(s512) = G_FREEZE %0 331 …vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY %1(s512)`
D	legalize-implicit-def.mir	`155 ; CHECK: [[DEF:%[0-9]+]]:_(s512) = G_IMPLICIT_DEF 156 ; CHECK: [[EXTRACT:%[0-9]+]]:_(s32) = G_EXTRACT [[DEF]](s512), 0 158 %0:_(s512) = G_IMPLICIT_DEF`
D	legalize-merge-values.mir	1218 ; CHECK: [[MV:%[0-9]+]]:_(s512) = G_MERGE_VALUES [[COPY]](s256), [[COPY1]](s256) 1219 …3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[MV]](s512) 1222 %2:_(s512) = G_MERGE_VALUES %0, %1 1234 …; CHECK: [[COPY:%[0-9]+]]:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vg… 1235 …; CHECK: [[COPY1:%[0-9]+]]:_(s512) = COPY $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23… 1236 ; CHECK: [[MV:%[0-9]+]]:_(s1024) = G_MERGE_VALUES [[COPY]](s512), [[COPY1]](s512) 1238 …%0:_(s512) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr1… 1239 …%1:_(s512) = COPY $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vg…
D	regbankselect-amdgcn.s.buffer.load.ll	`735 …; CHECK: [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFFE… 736 …:vgpr(s128), [[UV2:%[0-9]+]]:vgpr(s128), [[UV3:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s512) 764 …; GREEDY: [[MV:%[0-9]+]]:vgpr(s512) = G_MERGE_VALUES [[AMDGPU_BUFFER_LOAD]](s128), [[AMDGPU_BUFF… 765 …:vgpr(s128), [[UV2:%[0-9]+]]:vgpr(s128), [[UV3:%[0-9]+]]:vgpr(s128) = G_UNMERGE_VALUES [[MV]](s512)`
D	legalize-load-constant.mir	13965 ; CI: [[BITCAST:%[0-9]+]]:_(s512) = G_BITCAST [[LOAD]](<16 x s32>) 13966 …r4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](s512) 13970 ; VI: [[BITCAST:%[0-9]+]]:_(s512) = G_BITCAST [[LOAD]](<16 x s32>) 13971 …r4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](s512) 13975 ; GFX9: [[BITCAST:%[0-9]+]]:_(s512) = G_BITCAST [[LOAD]](<16 x s32>) 13976 …r4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](s512) 13980 ; CI-MESA: [[BITCAST:%[0-9]+]]:_(s512) = G_BITCAST [[LOAD]](<16 x s32>) 13981 …r4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](s512) 13985 ; GFX9-MESA: [[BITCAST:%[0-9]+]]:_(s512) = G_BITCAST [[LOAD]](<16 x s32>) 13986 …r4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[BITCAST]](s512) [all …]
/external/llvm-project/clang/test/CodeGen/X86/
D	x86_64-arguments.c	`468 } s512; typedef 470 s512 x55; 478 void f55(s512 x);`
/external/clang/test/CodeGen/
D	x86_64-arguments.c	`468 } s512; typedef 470 s512 x55; 477 void f55(s512 x);`
/external/autotest/client/tests/bonnie/
D	control.kernel_per-build_benchmarks	`22 job.run_test('bonnie', extra_args='-s512:256 -r0 -n128')`
/external/llvm-project/llvm/lib/Target/X86/
D	X86Schedule.td	`81 X86FoldableSchedWrite s512> { 86 X86FoldableSchedWrite ZMM = s512; // ZMM operations. 115 X86SchedWriteMoveLS s512> { 120 X86SchedWriteMoveLS ZMM = s512; // ZMM operations.`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
D	X86Schedule.td	`81 X86FoldableSchedWrite s512> { 86 X86FoldableSchedWrite ZMM = s512; // ZMM operations. 115 X86SchedWriteMoveLS s512> { 120 X86SchedWriteMoveLS ZMM = s512; // ZMM operations.`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
D	AArch64LegalizerInfo.cpp	`43 const LLT s512 = LLT::scalar(512); in AArch64LegalizerInfo() local 500 .clampScalar(BigTyIdx, s8, s512) in AArch64LegalizerInfo()`
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
D	AArch64LegalizerInfo.cpp	`47 const LLT s512 = LLT::scalar(512); in AArch64LegalizerInfo() local 540 .clampScalar(BigTyIdx, s8, s512) in AArch64LegalizerInfo()`

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