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/external/mesa3d/src/gallium/drivers/radeonsi/
Dcik_sdma.c61 struct si_texture *sdst = (struct si_texture *)dst; in si_sdma_v4_copy_texture() local
63 unsigned bpp = sdst->surface.bpe; in si_sdma_v4_copy_texture()
64 uint64_t dst_address = sdst->buffer.gpu_address + sdst->surface.u.gfx9.surf_offset; in si_sdma_v4_copy_texture()
66 unsigned dst_pitch = sdst->surface.u.gfx9.surf_pitch; in si_sdma_v4_copy_texture()
68 uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.gfx9.surf_slice_size) / bpp; in si_sdma_v4_copy_texture()
80 assert(sdst->surface.u.gfx9.surf_offset + dst_slice_pitch * bpp * (dstz + src_box->depth) <= in si_sdma_v4_copy_texture()
81 sdst->buffer.buf->size); in si_sdma_v4_copy_texture()
85 if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty, dstz, ssrc, src_level, src_box)) in si_sdma_v4_copy_texture()
88 dstx /= sdst->surface.blk_w; in si_sdma_v4_copy_texture()
89 dsty /= sdst->surface.blk_h; in si_sdma_v4_copy_texture()
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Dsi_dma_cs.c70 struct si_resource *sdst = si_resource(dst); in si_sdma_clear_buffer() local
86 util_range_add(dst, &sdst->valid_buffer_range, offset, offset + size); in si_sdma_clear_buffer()
88 offset += sdst->gpu_address; in si_sdma_clear_buffer()
93 si_need_dma_space(sctx, ncopy * 4, sdst, NULL); in si_sdma_clear_buffer()
113 si_need_dma_space(sctx, ncopy * 5, sdst, NULL); in si_sdma_clear_buffer()
134 struct si_resource *sdst = si_resource(dst); in si_sdma_copy_buffer() local
138 (ssrc->flags & RADEON_FLAG_ENCRYPTED) != (sdst->flags & RADEON_FLAG_ENCRYPTED)) { in si_sdma_copy_buffer()
146 util_range_add(dst, &sdst->valid_buffer_range, dst_offset, dst_offset + size); in si_sdma_copy_buffer()
148 dst_offset += sdst->gpu_address; in si_sdma_copy_buffer()
166 si_need_dma_space(sctx, ncopy * 5, sdst, ssrc); in si_sdma_copy_buffer()
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Dsi_cp_dma.c205 struct si_resource *sdst = si_resource(dst); in si_cp_dma_clear_buffer() local
206 uint64_t va = (sdst ? sdst->gpu_address : 0) + offset; in si_cp_dma_clear_buffer()
214 if (sdst) in si_cp_dma_clear_buffer()
215 util_range_add(dst, &sdst->valid_buffer_range, offset, offset + size); in si_cp_dma_clear_buffer()
218 if (sdst && !(user_flags & SI_CPDMA_SKIP_GFX_SYNC)) { in si_cp_dma_clear_buffer()
225 unsigned dma_flags = CP_DMA_CLEAR | (sdst ? 0 : CP_DMA_DST_IS_GDS); in si_cp_dma_clear_buffer()
237 if (sdst && cache_policy != L2_BYPASS) in si_cp_dma_clear_buffer()
238 sdst->TC_L2_dirty = true; in si_cp_dma_clear_buffer()
Dsi_buffer.c310 struct si_resource *sdst = si_resource(dst); in si_replace_buffer_storage() local
313 pb_reference(&sdst->buf, ssrc->buf); in si_replace_buffer_storage()
314 sdst->gpu_address = ssrc->gpu_address; in si_replace_buffer_storage()
315 sdst->b.b.bind = ssrc->b.b.bind; in si_replace_buffer_storage()
316 sdst->b.max_forced_staging_uploads = ssrc->b.max_forced_staging_uploads; in si_replace_buffer_storage()
317 sdst->max_forced_staging_uploads = ssrc->max_forced_staging_uploads; in si_replace_buffer_storage()
318 sdst->flags = ssrc->flags; in si_replace_buffer_storage()
320 assert(sdst->vram_usage == ssrc->vram_usage); in si_replace_buffer_storage()
321 assert(sdst->gart_usage == ssrc->gart_usage); in si_replace_buffer_storage()
322 assert(sdst->bo_size == ssrc->bo_size); in si_replace_buffer_storage()
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Dsi_fence.c185 struct si_multi_fence **sdst = (struct si_multi_fence **)dst; in si_fence_reference() local
188 if (pipe_reference(&(*sdst)->reference, &ssrc->reference)) { in si_fence_reference()
189 ws->fence_reference(&(*sdst)->gfx, NULL); in si_fence_reference()
190 ws->fence_reference(&(*sdst)->sdma, NULL); in si_fence_reference()
191 tc_unflushed_batch_token_reference(&(*sdst)->tc_token, NULL); in si_fence_reference()
192 si_resource_reference(&(*sdst)->fine.buf, NULL); in si_fence_reference()
193 FREE(*sdst); in si_fence_reference()
195 *sdst = ssrc; in si_fence_reference()
Dsi_test_dma.c202 struct si_texture *sdst; in si_test_dma() local
276 sdst = (struct si_texture *)dst; in si_test_dma()
284 array_mode_to_string(sscreen, &sdst->surface), tsrc.width0, tsrc.height0, in si_test_dma()
294 si_clear_buffer(sctx, dst, 0, sdst->surface.surf_size, &zero, 4, SI_COHERENCY_SHADER, false); in si_test_dma()
325 if (!ssrc->surface.is_linear && !sdst->surface.is_linear && rand() & 1) { in si_test_dma()
351 if (ssrc->surface.is_linear && !sdst->surface.is_linear && rand() % 4 == 0) { in si_test_dma()
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX7.rst428 …s_buffer_load_dword :ref:`sdst<amdgpu_synid7_sdst32_0>`, :ref:`sbase<amdgpu_synid7_…
429 …s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid7_sdst512_0>`, :ref:`sbase<amdgpu_synid7…
430 …s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`sbase<amdgpu_synid7_…
431 …s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid7_sdst128_0>`, :ref:`sbase<amdgpu_synid7…
432 …s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid7_sdst256_0>`, :ref:`sbase<amdgpu_synid7…
435 …s_load_dword :ref:`sdst<amdgpu_synid7_sdst32_0>`, :ref:`sbase<amdgpu_synid7_…
436 …s_load_dwordx16 :ref:`sdst<amdgpu_synid7_sdst512_0>`, :ref:`sbase<amdgpu_synid7…
437 …s_load_dwordx2 :ref:`sdst<amdgpu_synid7_sdst64_0>`, :ref:`sbase<amdgpu_synid7_…
438 …s_load_dwordx4 :ref:`sdst<amdgpu_synid7_sdst128_0>`, :ref:`sbase<amdgpu_synid7…
439 …s_load_dwordx8 :ref:`sdst<amdgpu_synid7_sdst256_0>`, :ref:`sbase<amdgpu_synid7…
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DAMDGPUAsmGFX8.rst440 …s_buffer_load_dword :ref:`sdst<amdgpu_synid8_sdst32_0>`, :ref:`sbase<amdgpu_synid8_…
441 …s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid8_sdst512_0>`, :ref:`sbase<amdgpu_synid8…
442 …s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`sbase<amdgpu_synid8_…
443 …s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid8_sdst128_0>`, :ref:`sbase<amdgpu_synid8…
444 …s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid8_sdst256_0>`, :ref:`sbase<amdgpu_synid8…
452 …s_load_dword :ref:`sdst<amdgpu_synid8_sdst32_0>`, :ref:`sbase<amdgpu_synid8_…
453 …s_load_dwordx16 :ref:`sdst<amdgpu_synid8_sdst512_0>`, :ref:`sbase<amdgpu_synid8…
454 …s_load_dwordx2 :ref:`sdst<amdgpu_synid8_sdst64_0>`, :ref:`sbase<amdgpu_synid8_…
455 …s_load_dwordx4 :ref:`sdst<amdgpu_synid8_sdst128_0>`, :ref:`sbase<amdgpu_synid8…
456 …s_load_dwordx8 :ref:`sdst<amdgpu_synid8_sdst256_0>`, :ref:`sbase<amdgpu_synid8…
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DAMDGPUAsmGFX9.rst590 …s_buffer_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_…
591 …s_buffer_load_dwordx16 :ref:`sdst<amdgpu_synid9_sdst512_0>`, :ref:`sbase<amdgpu_synid9…
592 …s_buffer_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_…
593 …s_buffer_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9…
594 …s_buffer_load_dwordx8 :ref:`sdst<amdgpu_synid9_sdst256_0>`, :ref:`sbase<amdgpu_synid9…
604 …s_load_dword :ref:`sdst<amdgpu_synid9_sdst32_0>`, :ref:`sbase<amdgpu_synid9_…
605 …s_load_dwordx16 :ref:`sdst<amdgpu_synid9_sdst512_0>`, :ref:`sbase<amdgpu_synid9…
606 …s_load_dwordx2 :ref:`sdst<amdgpu_synid9_sdst64_0>`, :ref:`sbase<amdgpu_synid9_…
607 …s_load_dwordx4 :ref:`sdst<amdgpu_synid9_sdst128_0>`, :ref:`sbase<amdgpu_synid9…
608 …s_load_dwordx8 :ref:`sdst<amdgpu_synid9_sdst256_0>`, :ref:`sbase<amdgpu_synid9…
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DAMDGPUAsmGFX10.rst786 …v_cmp_class_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
787 …v_cmp_class_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
788 …v_cmp_eq_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
789 …v_cmp_eq_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
790 …v_cmp_eq_i16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1…
791 …v_cmp_eq_i32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
792 …v_cmp_eq_u16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_1…
793 …v_cmp_eq_u32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
794 …v_cmp_f_f16_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
795 …v_cmp_f_f32_sdwa :ref:`sdst<amdgpu_synid10_wsdst>`, :ref:`src0<amdgpu_synid10_src32_0…
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Dgfx7_sdst512_0.rst10 sdst title
Dgfx8_sdst512_0.rst10 sdst title
Dgfx8_sdst256_0.rst10 sdst title
Dgfx8_sdst128_0.rst10 sdst title
Dgfx9_sdst256_0.rst10 sdst title
Dgfx10_sdst256_0.rst10 sdst title
Dgfx10_sdst512_0.rst10 sdst title
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td71 bits<7> sdst;
76 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
81 opName, (outs SReg_32:$sdst),
84 "$sdst, $src0", pattern> {
85 let Constraints = !if(tied_in, "$sdst = $sdst_in", "");
90 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
91 "$sdst, $src0", pattern>;
107 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
108 "$sdst, $src0", pattern
113 opName, (outs SReg_64:$sdst), (ins SReg_64:$src0),
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DSMInstructions.td60 bits<7> sdst;
113 (outs dstClass:$sdst),
115 " $sdst, $sbase, $offset$glc$dlc", []> {
124 (outs dstClass:$sdst),
126 " $sdst, $sbase, $offset$glc$dlc", []> {
161 opName, (outs SReg_64_XEXEC:$sdst), (ins),
162 " $sdst", [(set i64:$sdst, (node))]> {
193 opName, (outs SReg_32_XM0_XEXEC:$sdst), (ins),
194 " $sdst", [(set i32:$sdst, (node))]> {
229 !if(isRet, (outs dataClass:$sdst), (outs)),
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DSOPInstructions.td71 bits<7> sdst;
76 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
81 opName, (outs SReg_32:$sdst),
84 "$sdst, $src0", pattern> {
85 let Constraints = !if(tied_in, "$sdst = $sdst_in", "");
90 opName, (outs SReg_32:$sdst), (ins SReg_32:$src0),
91 "$sdst, $src0", pattern>;
100 // Special case for movreld where sdst is treated as a use operand.
102 opName, (outs), (ins SReg_32:$sdst, SSrc_b32:$src0),
103 "$sdst, $src0", pattern>;
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DSMInstructions.td69 bits<7> sdst;
122 (outs dstClass:$sdst),
124 " $sdst, $sbase, $offset$glc$dlc", []> {
133 (outs dstClass:$sdst),
135 " $sdst, $sbase, $offset$glc$dlc", []> {
170 opName, (outs SReg_64_XEXEC:$sdst), (ins),
171 " $sdst", [(set i64:$sdst, (node))]> {
202 opName, (outs SReg_32_XM0_XEXEC:$sdst), (ins),
203 " $sdst", [(set i32:$sdst, (node))]> {
238 !if(isRet, (outs dataClass:$sdst), (outs)),
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/external/icu/icu4j/main/classes/localespi/src/com/ibm/icu/impl/javaspi/util/
DTimeZoneNameProviderICU.java35 String sdst = tznames.getDisplayName(canonicalID, NameType.SHORT_DAYLIGHT, date); in getDisplayName() local
37 if (lstd != null && ldst != null && sstd != null && sdst != null) { in getDisplayName()
43 dispName = daylight ? sdst : sstd; in getDisplayName()
/external/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td182 bits<7> sdst;
187 let Inst{22-16} = sdst;
192 bits<7> sdst;
198 let Inst{22-16} = sdst;
214 bits <7> sdst;
218 let Inst{22-16} = sdst;
224 bits <7> sdst = 0;
229 let Inst{22-16} = sdst;
245 bits<7> sdst;
250 let Inst{21-15} = sdst;
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DVIInstrFormats.td94 bits<7> sdst;
98 let Inst{12-6} = sdst;
147 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
149 bits<8> sdst;
151 let Inst{7-0} = sdst;
162 bits<7> sdst;
167 let Inst{14-8} = sdst;
DSIInstrInfo.td756 op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0),
757 opName#" $sdst, $src0", pattern
761 op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0),
762 opName#" $sdst, $src0", pattern
767 def "" : SOP1_Pseudo <opName, (outs SReg_64:$sdst), (ins), pattern>;
769 def _si : SOP1_Real_si <op, opName, (outs SReg_64:$sdst), (ins),
770 opName#" $sdst"> {
774 def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$sdst), (ins),
775 opName#" $sdst"> {
786 let sdst = 0;
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