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Searched refs:shld (Results 1 – 25 of 55) sorted by relevance

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/external/boringssl/win-x86/crypto/fipsmodule/
Dsha1-586.asm2695 shld eax,eax,5
2710 shld edi,edi,5
2723 shld edx,edx,5
2737 shld ecx,ecx,5
2752 shld ebx,ebx,5
2767 shld eax,eax,5
2780 shld edi,edi,5
2794 shld edx,edx,5
2809 shld ecx,ecx,5
2824 shld ebx,ebx,5
[all …]
/external/openscreen/third_party/boringssl/win-x86/crypto/fipsmodule/
Dsha1-586.asm2695 shld eax,eax,5
2710 shld edi,edi,5
2723 shld edx,edx,5
2737 shld ecx,ecx,5
2752 shld ebx,ebx,5
2767 shld eax,eax,5
2780 shld edi,edi,5
2794 shld edx,edx,5
2809 shld ecx,ecx,5
2824 shld ebx,ebx,5
[all …]
/external/llvm/test/CodeGen/X86/
D2006-01-19-ISelFoldingBug.ll2 ; RUN: grep shld | count 1
4 ; Check that the isel does not fold the shld, which already folds a load
Dx86-64-double-shifts-Oz-Os-O2.ll4 ; Verify that we generate shld insruction when we are optimizing for size,
26 ; Verify that we generate shld insruction when we are optimizing for size,
47 ; Verify that we do not generate shld insruction when we are not optimizing
Dx86-64-double-shifts-var.ll20 ; double precision shift instructions we do not generate 'shld' or 'shrd'
30 ; CHECK-NOT: shld
Dshift-coalesce.ll2 ; RUN: grep "shld.*cl"
Dx86-64-double-precision-shift-left.ll4 ; of instructions with lower latencies instead of shld instruction.
Drot64.ll4 ; RUN: grep shld %t | count 2
/external/openscreen/third_party/boringssl/win-x86_64/crypto/fipsmodule/
Dsha1-x86_64.asm2767 shld eax,eax,5
2781 shld ebp,ebp,5
2795 shld edx,edx,5
2810 shld ecx,ecx,5
2822 shld ebx,ebx,5
2836 shld eax,eax,5
2850 shld ebp,ebp,5
2865 shld edx,edx,5
2878 shld ecx,ecx,5
2892 shld ebx,ebx,5
[all …]
/external/boringssl/win-x86_64/crypto/fipsmodule/
Dsha1-x86_64.asm2767 shld eax,eax,5
2781 shld ebp,ebp,5
2795 shld edx,edx,5
2810 shld ecx,ecx,5
2822 shld ebx,ebx,5
2836 shld eax,eax,5
2850 shld ebp,ebp,5
2865 shld edx,edx,5
2878 shld ecx,ecx,5
2892 shld ebx,ebx,5
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dx86-64-double-shifts-Oz-Os-O2.ll5 ; Verify that we generate shld insruction when we are optimizing for size,
31 ; Verify that we generate shld insruction when we are optimizing for size,
69 ; Verify that we do not generate shld insruction when we are not optimizing
Dx86-64-double-shifts-var.ll19 ; double precision shift instructions we do not generate 'shld' or 'shrd'
29 ; CHECK-NOT: shld
D2006-01-19-ISelFoldingBug.ll4 ; Check that the isel does not fold the shld, which already folds a load
Dshift-coalesce.ll18 ; CHECK-NEXT: shld edx, esi, cl
Dx86-64-double-precision-shift-left.ll6 ; of instructions with lower latencies instead of shld instruction.
Drot32.ll288 ; shld-label: xunp:
289 ; shld: shldl $25
/external/llvm/test/MC/X86/
Dintel-syntax.s379 shld DX, BX define
380 shld DX, BX, CL define
381 shld DX, BX, 1 define
382 shld [RAX], BX label
383 shld [RAX], BX, CL label
Dx86-64.s378 shld %bx, %dx label
379 shld %cl, %bx, %dx label
380 shld $1, %bx, %dx label
381 shld %bx, (%rax) label
382 shld %cl, %bx, (%rax) label
/external/llvm-project/llvm/test/MC/X86/
Dintel-syntax.s445 shld DX, BX define
446 shld DX, BX, CL define
447 shld DX, BX, 1 define
448 shld [RAX], BX label
449 shld [RAX], BX, CL label
Dx86-64.s374 shld %bx, %dx label
375 shld %cl, %bx, %dx label
376 shld $1, %bx, %dx label
377 shld %bx, (%rax) label
378 shld %cl, %bx, (%rax) label
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td663 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
673 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
683 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
697 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
711 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
725 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
741 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
750 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
759 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
771 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td693 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
705 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
715 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
731 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
745 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
759 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
776 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
785 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
794 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
805 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrShiftRotate.td663 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
673 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
683 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
697 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
711 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
725 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
741 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
750 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
759 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
771 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
[all …]
/external/swiftshader/third_party/subzero/src/
DIceAssemblerX86Base.h677 void shld(Type Ty, GPRRegister dst, GPRRegister src);
678 void shld(Type Ty, GPRRegister dst, GPRRegister src, const Immediate &imm);
679 void shld(Type Ty, const Address &operand, GPRRegister src);
/external/mesa3d/src/mesa/x86/
Dassyntax.h648 #define SHLD_L(a,b,c) CHOICE(shldl ARG3(a,b,c), shldl ARG3(a,b,c), _LTOG shld ARG3(c,b,a))
649 #define SHLD2_L(a,b) CHOICE(shldl ARG2(a,b), shldl ARG3(CL,a,b), _LTOG shld ARG3(b,a,CL))
650 #define SHLD_W(a,b,c) CHOICE(shldw ARG3(a,b,c), shldw ARG3(a,b,c), _WTOG shld ARG3(c,b,a))
651 #define SHLD2_W(a,b) CHOICE(shldw ARG2(a,b), shldw ARG3(CL,a,b), _WTOG shld ARG3(b,a,CL))
1361 #define SHLD_L(a,b,c) shld
1362 #define SHLD2_L(a,b) shld L_(b), L_(a)
1363 #define SHLD_W(a,b,c) shld
1364 #define SHLD2_W(a,b) shld W_(b), W_(a)

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