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Searched refs:stnt1h (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dstnt1h-diagnostics.s6 stnt1h z23.h, p0, [x13, #-9, MUL VL] label
11 stnt1h z29.h, p0, [x3, #8, MUL VL] label
20 stnt1h z0.b, p0, [x0] label
25 stnt1h z0.s, p0, [x0] label
30 stnt1h z0.d, p0, [x0] label
39 stnt1h z27.h, p8, [x0] label
44 stnt1h z0.h, p0/z, [x0] label
49 stnt1h z0.h, p0/m, [x0] label
54 stnt1h z0.h, p7.b, [x0] label
59 stnt1h z0.h, p7.q, [x0] label
[all …]
Dstnt1h.s10 stnt1h z0.h, p0, [x0] label
16 stnt1h { z0.h }, p0, [x0] label
22 stnt1h { z23.h }, p3, [x13, #-8, mul vl] label
28 stnt1h { z21.h }, p5, [x10, #7, mul vl] label
34 stnt1h { z0.h }, p0, [x0, x0, lsl #1] label
/external/llvm-project/llvm/test/MC/AArch64/SVE2/
Dstnt1h.s10 stnt1h z0.s, p0, [z1.s] label
16 stnt1h z31.s, p7, [z31.s, xzr] label
22 stnt1h z31.s, p7, [z31.s, x0] label
28 stnt1h z0.d, p0, [z1.d] label
34 stnt1h z31.d, p7, [z31.d, xzr] label
40 stnt1h z31.d, p7, [z31.d, x0] label
46 stnt1h { z0.s }, p0, [z1.s] label
52 stnt1h { z31.s }, p7, [z31.s, xzr] label
58 stnt1h { z31.s }, p7, [z31.s, x0] label
64 stnt1h { z0.d }, p0, [z1.d] label
[all …]
Dstnt1h-diagnostics.s7 stnt1h { z0.b }, p0, [z0.s] label
12 stnt1h { z0.h }, p0, [z0.s] label
21 stnt1h { z0.s }, p0, [z0.b] label
26 stnt1h { z0.d }, p0, [z0.h] label
35 stnt1h { z0.d }, p0, [z0.d, z1.d] label
44 stnt1h { z27.d }, p8, [z0.d] label
53 stnt1h { }, p0, [z0.d] label
58 stnt1h { z0.d, z1.d }, p0, [z0.d] label
63 stnt1h { v0.2d }, p0, [z0.d] label
73 stnt1h { z0.d }, p0, [z0.d, x0] label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve2-intrinsics-nt-scatter-stores-64bit-scaled-offset.ll11 ; stnt1h { z0.d }, p0, [z0.d, x0]
17 ; CHECK-NEXT: stnt1h { z0.d }, p0, [z1.d, x0]
Dsve2-intrinsics-nt-scatter-stores-64bit-unscaled-offset.ll9 ; e.g. stnt1h { z0.d }, p0, [z1.d, x0]
26 ; CHECK: stnt1h { z0.d }, p0, [z1.d, x0]
Dsve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll73 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
87 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
101 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
Dsve2-intrinsics-nt-scatter-stores-32bit-unscaled-offset.ll10 ; e.g. stnt1h { z0.d }, p0, [z1.d, x0]
29 ; CHECK: stnt1h { z0.s }, p0, [z1.s, x0]
Dsve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll112 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #7, mul vl]
129 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
146 ; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, #2, mul vl]
Dsve2-intrinsics-nt-scatter-stores-vector-base-scalar-offset.ll40 ; CHECK: stnt1h { z0.s }, p0, [z1.s, x0]
52 ; CHECK: stnt1h { z0.d }, p0, [z1.d, x0]
Dsve-intrinsics-stores.ll398 ; CHECK: stnt1h { z0.h }, p0, [x0]
408 ; CHECK: stnt1h { z0.h }, p0, [x0]
418 ; CHECK: stnt1h { z0.h }, p0, [x0]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmMatcher.inc18800 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZRI, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
18801 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_…
18802 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
18803 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZRI, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__R…
18804 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyRe…
18805 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyRe…
18806 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZRR, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Reg1…
18807 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_…
18808 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_…
18809 …{ 5580 /* stnt1h */, AArch64::STNT1H_ZRR, Convert__SVEVectorList1161_0__SVEPredicate3bAnyReg1_1__R…
[all …]
DAArch64GenAsmWriter.inc22770 /* 12725 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
22771 /* 12749 */ "stnt1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
22772 /* 12775 */ "stnt1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
DAArch64GenAsmWriter1.inc23491 /* 12703 */ "stnt1h $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]\0"
23492 /* 12727 */ "stnt1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]\0"
23493 /* 12753 */ "stnt1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]\0"
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td697 defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
703 defm STNT1H_ZRR : sve_mem_cstnt_ss<0b01, "stnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
1578 defm STNT1H_ZZR_S : sve2_mem_sstnt_vs<0b011, "stnt1h", Z_s, ZPR32>;
1582 defm STNT1H_ZZR_D : sve2_mem_sstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
/external/vixl/src/aarch64/
Dmacro-assembler-sve-aarch64.cc1615 &MacroAssembler::stnt1h, in Stnt1h()
Dassembler-aarch64.h5531 void stnt1h(const ZRegister& zt,
Dassembler-sve-aarch64.cc5180 void Assembler::stnt1h(const ZRegister& zt, in stnt1h() function in vixl::aarch64::Assembler
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SVEInstrInfo.td1037 defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
1043 defm STNT1H_ZRR : sve_mem_cstnt_ss<0b01, "stnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
2757 defm STNT1H_ZZR_S : sve2_mem_sstnt_vs_32_ptrs<0b011, "stnt1h", AArch64stnt1_scatter, nxv4i16>;
2761 defm STNT1H_ZZR_D : sve2_mem_sstnt_vs_64_ptrs<0b010, "stnt1h", AArch64stnt1_scatter, nxv2i16>;
/external/vixl/test/aarch64/
Dtest-disasm-sve-aarch64.cc4632 COMPARE_PREFIX(stnt1h(z30.VnH(), in TEST()
4651 COMPARE_PREFIX(stnt1h(z26.VnH(), in TEST()