Home
last modified time | relevance | path

Searched refs:umin (Results 1 – 25 of 371) sorted by relevance

12345678910>>...15

/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dreduce-umin.ll8 …n estimated cost of 2 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> und…
9 … estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> und…
10 … estimated cost of 35 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> und…
11 … estimated cost of 79 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> und…
12 …stimated cost of 167 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> u…
16 …n estimated cost of 3 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> und…
17 … estimated cost of 17 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> und…
18 … estimated cost of 31 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> und…
19 … estimated cost of 76 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> und…
20 …stimated cost of 178 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> u…
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-umin.ll14 …n estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> und…
15 … estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> und…
16 … estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> und…
17 … estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> und…
18 …estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> u…
22 …n estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> und…
23 … estimated cost of 13 for instruction: %V2 = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> und…
24 … estimated cost of 24 for instruction: %V4 = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> und…
25 … estimated cost of 46 for instruction: %V8 = call i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> und…
26 …estimated cost of 90 for instruction: %V16 = call i64 @llvm.vector.reduce.umin.v16i64(<16 x i64> u…
[all …]
Darith-uminmax.ll207 declare i64 @llvm.umin.i64(i64, i64)
208 declare <2 x i64> @llvm.umin.v2i64(<2 x i64>, <2 x i64>)
209 declare <4 x i64> @llvm.umin.v4i64(<4 x i64>, <4 x i64>)
210 declare <8 x i64> @llvm.umin.v8i64(<8 x i64>, <8 x i64>)
212 declare i32 @llvm.umin.i32(i32, i32)
213 declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
214 declare <8 x i32> @llvm.umin.v8i32(<8 x i32>, <8 x i32>)
215 declare <16 x i32> @llvm.umin.v16i32(<16 x i32>, <16 x i32>)
217 declare i16 @llvm.umin.i16(i16, i16)
218 declare <8 x i16> @llvm.umin.v8i16(<8 x i16>, <8 x i16>)
[all …]
/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dumin.s10 umin z0.b, z0.b, #0 label
16 umin z31.b, z31.b, #255 label
22 umin z0.b, z0.b, #0 label
28 umin z31.b, z31.b, #255 label
34 umin z0.b, z0.b, #0 label
40 umin z31.b, z31.b, #255 label
46 umin z0.b, z0.b, #0 label
52 umin z31.b, z31.b, #255 label
58 umin z31.b, p7/m, z31.b, z31.b label
64 umin z31.h, p7/m, z31.h, z31.h label
[all …]
Dumin-diagnostics.s3 umin z0.b, z0.b, #-1 label
8 umin z31.b, z31.b, #256 label
13 umin z0.b, p8/m, z0.b, z0.b label
23 umin z31.b, z31.b, #255 label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dumed3.ll102 define internal i32 @umin(i32 %x, i32 %y) #2 {
159 %tmp0 = call i32 @umin(i32 %x, i32 %y)
161 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
171 %tmp0 = call i32 @umin(i32 %x, i32 %y)
173 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
183 %tmp0 = call i32 @umin(i32 %x, i32 %y)
185 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
195 %tmp0 = call i32 @umin(i32 %x, i32 %y)
197 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
207 %tmp0 = call i32 @umin(i32 %y, i32 %x)
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/AArch64/
Dmin-max.ll4 ; COST-LABEL: umin.v8i8
5 …ound an estimated cost of 1 for instruction: %res = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %v0, …
7 ; CODE-LABEL: umin.v8i8
9 ; CODE-NEXT: umin v{{.*}}.8b, v{{.*}}.8b, v{{.*}}.8b
12 declare <8 x i8> @llvm.umin.v8i8(<8 x i8>, <8 x i8>)
13 define <8 x i8> @umin.v8i8(<8 x i8> %v0, <8 x i8> %v1) {
14 %res = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %v0, <8 x i8> %v1)
18 ; COST-LABEL: umin.v9i8
19 …ound an estimated cost of 1 for instruction: %res = call <9 x i8> @llvm.umin.v9i8(<9 x i8> %v0, …
21 ; CODE-LABEL: umin.v9i8
[all …]
Dvector-reduce.ll49 ; COST-LABEL: umin.i8.v8i8
50 ; COST: Found an estimated cost of 216 for instruction: %r = call i8 @llvm.vector.reduce.umin…
51 ; CODE-LABEL: umin.i8.v8i8
53 define i8 @umin.i8.v8i8(<8 x i8> %v) {
54 %r = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %v)
58 ; COST-LABEL: umin.i8.v16i8
59 ; COST: Found an estimated cost of 608 for instruction: %r = call i8 @llvm.vector.reduce.umin…
60 ; CODE-LABEL: umin.i8.v16i8
62 define i8 @umin.i8.v16i8(<16 x i8> %v) {
63 %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %v)
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dumed3.ll119 define internal i32 @umin(i32 %x, i32 %y) #2 {
176 %tmp0 = call i32 @umin(i32 %x, i32 %y)
178 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
188 %tmp0 = call i32 @umin(i32 %x, i32 %y)
190 %tmp2 = call i32 @umin(i32 %tmp1, i32 %z)
200 %tmp0 = call i32 @umin(i32 %x, i32 %y)
202 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
212 %tmp0 = call i32 @umin(i32 %x, i32 %y)
214 %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
224 %tmp0 = call i32 @umin(i32 %y, i32 %x)
[all …]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Darith-umin.ll23 declare i64 @llvm.umin.i64(i64, i64)
24 declare i32 @llvm.umin.i32(i32, i32)
25 declare i16 @llvm.umin.i16(i16, i16)
26 declare i8 @llvm.umin.i8 (i8 , i8 )
46 ; SSE-NEXT: [[R0:%.*]] = call i64 @llvm.umin.i64(i64 [[A0]], i64 [[B0]])
47 ; SSE-NEXT: [[R1:%.*]] = call i64 @llvm.umin.i64(i64 [[A1]], i64 [[B1]])
48 ; SSE-NEXT: [[R2:%.*]] = call i64 @llvm.umin.i64(i64 [[A2]], i64 [[B2]])
49 ; SSE-NEXT: [[R3:%.*]] = call i64 @llvm.umin.i64(i64 [[A3]], i64 [[B3]])
50 ; SSE-NEXT: [[R4:%.*]] = call i64 @llvm.umin.i64(i64 [[A4]], i64 [[B4]])
51 ; SSE-NEXT: [[R5:%.*]] = call i64 @llvm.umin.i64(i64 [[A5]], i64 [[B5]])
[all …]
/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Dminmax-intrinsics.ll6 declare i32 @llvm.umin.i32(i32, i32)
21 define i32 @umin(i32 %x, i32 %y) {
22 ; CHECK-LABEL: 'umin'
23 ; CHECK-NEXT: Classifying expressions for: @umin
24 ; CHECK-NEXT: %z = call i32 @llvm.umin.i32(i32 %x, i32 %y)
25 ; CHECK-NEXT: --> (%x umin %y) U: full-set S: full-set
26 ; CHECK-NEXT: Determining loop execution counts for: @umin
28 %z = call i32 @llvm.umin.i32(i32 %x, i32 %y)
59 ; CHECK-NEXT: %z = call i32 @llvm.umin.i32(i32 %y, i32 20)
60 ; CHECK-NEXT: --> (20 umin (10 umax %x)) U: [10,21) S: [10,21)
[all …]
Dmax-expr-cache.ll134 …umin (1 + (256 umin (1 + (256 umin (1 + (256 umin (1 + (256 umin (1 + (256 umin (1 + (256 umin (1 …
Dtrip-count15.ll9 ; CHECK-NEXT: --> (4096 umin %n) U: [0,4097) S: [0,4097)
11 ; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,4098) S: [0,4098) Exits: (1 + (4096 umin %n))<nuw><nsw> L…
13 ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4099) S: [1,4099) Exits: (2 + (4096 umin %n))<nuw><nsw> L…
15 ; CHECK-NEXT: Loop %loop: backedge-taken count is (1 + (4096 umin %n))<nuw><nsw>
17 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (1 + (4096 umin %n))<nuw><nsw>
39 ; CHECK-NEXT: --> (4096 umin %n) U: [0,4097) S: [0,4097)
41 ; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,4098) S: [0,4098) Exits: (1 + (4096 umin %n))<nuw><nsw> L…
43 ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4099) S: [1,4099) Exits: (2 + (4096 umin %n))<nuw><nsw> L…
45 ; CHECK-NEXT: Loop %loop: backedge-taken count is (1 + (4096 umin %n))<nuw><nsw>
47 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (1 + (4096 umin %n))<nuw><nsw>
/external/capstone/suite/MC/AArch64/
Dneon-max-min.s.cs20 0x20,0x6c,0x22,0x2e = umin v0.8b, v1.8b, v2.8b
21 0x20,0x6c,0x22,0x6e = umin v0.16b, v1.16b, v2.16b
22 0x20,0x6c,0x62,0x2e = umin v0.4h, v1.4h, v2.4h
23 0x20,0x6c,0x62,0x6e = umin v0.8h, v1.8h, v2.8h
24 0x20,0x6c,0xa2,0x2e = umin v0.2s, v1.2s, v2.2s
25 0x20,0x6c,0xa2,0x6e = umin v0.4s, v1.4s, v2.4s
/external/llvm-project/llvm/test/Transforms/InstSimplify/
Dmaxmin_intrinsics.ll14 declare i8 @llvm.umin.i8(i8, i8)
15 declare <2 x i8> @llvm.umin.v2i8(<2 x i8>, <2 x i8>)
46 %r = call <2 x i8> @llvm.umin.v2i8(<2 x i8> %x, <2 x i8> %x)
102 %r = call <2 x i8> @llvm.umin.v2i8(<2 x i8> %x, <2 x i8> undef)
110 %r = call <2 x i8> @llvm.umin.v2i8(<2 x i8> %x, <2 x i8> poison)
166 %r = call i8 @llvm.umin.i8(i8 0, i8 %x)
174 %r = call <2 x i8> @llvm.umin.v2i8(<2 x i8> %x, <2 x i8> zeroinitializer)
230 %r = call i8 @llvm.umin.i8(i8 255, i8 %x)
238 %r = call <2 x i8> @llvm.umin.v2i8(<2 x i8> %x, <2 x i8> <i8 255, i8 255>)
270 %r = call <2 x i8> @llvm.umin.v2i8(<2 x i8> %x, <2 x i8> <i8 undef, i8 0>)
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-max-min.s53 umin v0.8b, v1.8b, v2.8b
54 umin v0.16b, v1.16b, v2.16b
55 umin v0.4h, v1.4h, v2.4h
56 umin v0.8h, v1.8h, v2.8h
57 umin v0.2s, v1.2s, v2.2s
58 umin v0.4s, v1.4s, v2.4s
/external/llvm/test/MC/AArch64/
Dneon-max-min.s53 umin v0.8b, v1.8b, v2.8b
54 umin v0.16b, v1.16b, v2.16b
55 umin v0.4h, v1.4h, v2.4h
56 umin v0.8h, v1.8h, v2.8h
57 umin v0.2s, v1.2s, v2.2s
58 umin v0.4s, v1.4s, v2.4s
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-minmaxv.ll15 declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>)
16 declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>)
17 declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>)
98 %r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %arr.load)
106 %r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %arr.load)
114 %r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %arr.load)
158 declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)
162 ; CHECK: umin [[V0:v[0-9]+]].8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
165 %r = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %arr.load)
169 declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
[all …]
Dsve-fixed-length-int-minmax.ll1148 ; CHECK: umin v0.8b, v0.8b, v1.8b
1150 %res = call <8 x i8> @llvm.umin.v8i8(<8 x i8> %op1, <8 x i8> %op2)
1157 ; CHECK: umin v0.16b, v0.16b, v1.16b
1159 %res = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %op1, <16 x i8> %op2)
1168 ; CHECK-NEXT: umin [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
1173 %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2)
1183 ; VBITS_GE_512-NEXT: umin [[RES:z[0-9]+]].b, [[PG]]/m, [[OP1]].b, [[OP2]].b
1194 ; VBITS_EQ_256-DAG: umin [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP1_LO]].b, [[OP2_LO]].b
1195 ; VBITS_EQ_256-DAG: umin [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP1_HI]].b, [[OP2_HI]].b
1200 %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> %op2)
[all …]
/external/llvm-project/llvm/test/Transforms/IndVarSimplify/
Dbackedge-on-min-max.ll235 %umin.cmp = icmp ult i32 %a_len, %n
236 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
237 %entry.cond = icmp ult i32 5, %umin
253 %be.cond = icmp ult i32 %idx.inc, %umin
263 %umin.cmp = icmp ult i32 %a_len, %n
264 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
265 %entry.cond = icmp ult i32 5, %umin
281 %be.cond = icmp ult i32 %idx.inc, %umin
291 %umin.cmp = icmp ult i32 42, %n
292 %umin = select i1 %umin.cmp, i32 42, i32 %n
[all …]
/external/llvm/test/Transforms/IndVarSimplify/
Dbackedge-on-min-max.ll235 %umin.cmp = icmp ult i32 %a_len, %n
236 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
237 %entry.cond = icmp ult i32 5, %umin
253 %be.cond = icmp ult i32 %idx.inc, %umin
263 %umin.cmp = icmp ult i32 %a_len, %n
264 %umin = select i1 %umin.cmp, i32 %a_len, i32 %n
265 %entry.cond = icmp ult i32 5, %umin
281 %be.cond = icmp ult i32 %idx.inc, %umin
291 %umin.cmp = icmp ult i32 42, %n
292 %umin = select i1 %umin.cmp, i32 42, i32 %n
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dumin.ll7 declare i8 @llvm.umin.i8(i8, i8)
8 declare i16 @llvm.umin.i16(i16, i16)
9 declare i24 @llvm.umin.i24(i24, i24)
10 declare i32 @llvm.umin.i32(i32, i32)
11 declare i64 @llvm.umin.i64(i64, i64)
12 declare i128 @llvm.umin.i128(i128, i128)
14 declare <1 x i32> @llvm.umin.v1i32(<1 x i32>, <1 x i32>)
15 declare <2 x i32> @llvm.umin.v2i32(<2 x i32>, <2 x i32>)
16 declare <3 x i32> @llvm.umin.v3i32(<3 x i32>, <3 x i32>)
17 declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>)
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dcommutative-intrinsics.ll31 define <3 x i35> @umin(<3 x i35> %x) {
32 ; CHECK-LABEL: @umin(
33 ; CHECK-NEXT: [[R:%.*]] = call <3 x i35> @llvm.umin.v3i35(<3 x i35> [[X:%.*]], <3 x i35> <i35 un…
36 %r = call <3 x i35> @llvm.umin.v3i35(<3 x i35> <i35 undef, i35 42, i35 43>, <3 x i35> %x)
79 declare <3 x i35> @llvm.umin.v3i35(<3 x i35>, <3 x i35>)
/external/llvm-project/llvm/test/Transforms/BDCE/
Dintrinsics.ll5 declare i8 @llvm.umin.i8(i8, i8)
28 define i8 @umin(i8 %x, i8 %y, i1 %a, i1 %b) {
29 ; CHECK-LABEL: @umin(
34 ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[X2]], i8 [[Y2]])
42 %m = call i8 @llvm.umin.i8(i8 %x2, i8 %y2)
/external/llvm-project/libclc/generic/lib/atomic/
Datomic_min.cl9 IMPL(unsigned int, global, umin)
11 IMPL(unsigned int, local, umin)

12345678910>>...15