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/external/llvm-project/llvm/test/MC/AArch64/SVE/
Duxtb.s10 uxtb z0.h, p0/m, z0.h label
16 uxtb z0.s, p0/m, z0.s label
22 uxtb z0.d, p0/m, z0.d label
28 uxtb z31.h, p7/m, z31.h label
34 uxtb z31.s, p7/m, z31.s label
40 uxtb z31.d, p7/m, z31.d label
56 uxtb z4.d, p7/m, z31.d label
68 uxtb z4.d, p7/m, z31.d label
/external/llvm-project/llvm/test/CodeGen/ARM/
Dfast-isel-fold.ll11 ; ARM-NOT: uxtb
15 ; THUMB-NOT: uxtb
40 ; ARM-NOT: uxtb
44 ; THUMB-NOT: uxtb
Dhoist-and-by-const-from-shl-in-eqcmp-zero.ll23 ; ARM-NEXT: uxtb r1, r1
24 ; ARM-NEXT: uxtb r0, r0
32 ; THUMB6-NEXT: uxtb r1, r1
33 ; THUMB6-NEXT: uxtb r0, r0
43 ; THUMB7-NEXT: uxtb r1, r1
44 ; THUMB7-NEXT: uxtb r0, r0
52 ; THUMB8-NEXT: uxtb r0, r0
53 ; THUMB8-NEXT: uxtb r1, r1
67 ; ARM-NEXT: uxtb r1, r1
68 ; ARM-NEXT: uxtb r0, r0
[all …]
Datomic-cmpxchg.ll39 ; CHECK-ARMV6: uxtb r1, r1
57 ; CHECK-THUMBV6-NEXT: uxtb r1, r4
64 ; CHECK-ARMV7: uxtb r1, r1
80 ; CHECK-THUMBV7: uxtb r1, r1
Dusub_sat_plus.ll146 ; CHECK-T1-NEXT: uxtb r2, r1
153 ; CHECK-T1-NEXT: uxtb r0, r0
159 ; CHECK-T2-NEXT: uxtb r3, r3
164 ; CHECK-T2-NEXT: uxtb r0, r0
170 ; CHECK-ARM-NEXT: uxtb r3, r3
174 ; CHECK-ARM-NEXT: uxtb r0, r0
Dhoist-and-by-const-from-lshr-in-eqcmp-zero.ll23 ; ARM-NEXT: uxtb r1, r1
26 ; ARM-NEXT: uxtb r0, r0
32 ; THUMB6-NEXT: uxtb r1, r1
42 ; THUMB78-NEXT: uxtb r1, r1
45 ; THUMB78-NEXT: uxtb r0, r0
57 ; ARM-NEXT: uxtb r1, r1
64 ; THUMB6-NEXT: uxtb r1, r1
74 ; THUMB78-NEXT: uxtb r1, r1
88 ; ARM-NEXT: uxtb r1, r1
97 ; THUMB6-NEXT: uxtb r1, r1
[all …]
/external/llvm/test/CodeGen/ARM/
Dfast-isel-fold.ll11 ; ARM-NOT: uxtb
15 ; THUMB-NOT: uxtb
40 ; ARM-NOT: uxtb
44 ; THUMB-NOT: uxtb
Duxt_rot.ll24 ; CHECK: uxtb
25 ; CHECK-NOT: uxtb
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daddsub_ext.ll28 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
29 ; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
34 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
35 ; GISEL: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
41 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
42 ; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
47 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
48 ; GISEL: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
76 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxtb
106 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
[all …]
Dcmp-to-cmn.ll42 ; CHECK: cmn x0, w1, uxtb
89 ; CHECK: cmn w0, w1, uxtb
153 ; CHECK: cmn x1, w0, uxtb
165 ; CHECK: cmn w1, w0, uxtb
178 ; CHECK-NEXT: cmn w8, w0, uxtb
192 ; CHECK-NEXT: cmn w8, w0, uxtb
240 ; CHECK: cmn x0, w1, uxtb
287 ; CHECK: cmn w0, w1, uxtb
351 ; CHECK: cmn x1, w0, uxtb
363 ; CHECK: cmn w1, w0, uxtb
[all …]
Dsve-intrinsics-conversion.ll85 ; CHECK: uxtb z0.h, p0/m, z1.h
87 %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16> %a,
95 ; CHECK: uxtb z0.s, p0/m, z1.s
97 %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32> %a,
105 ; CHECK: uxtb z0.d, p0/m, z1.d
107 %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64> %a,
158 declare <vscale x 8 x i16> @llvm.aarch64.sve.uxtb.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, <v…
159 declare <vscale x 4 x i32> @llvm.aarch64.sve.uxtb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <v…
160 declare <vscale x 2 x i64> @llvm.aarch64.sve.uxtb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <v…
Darm64-ldxr-stxr.ll40 ; CHECK-NOT: uxtb
46 ; GISEL-NOT: uxtb
65 ; GISEL-NOT: uxtb
84 ; GISEL-NOT: uxtb
101 ; GISEL-NOT: uxtb
117 ; CHECK-NOT: uxtb
121 ; GISEL-NOT: uxtb
215 ; CHECK-NOT: uxtb
288 ; CHECK-NOT: uxtb
292 ; GISEL-NOT: uxtb
/external/llvm-project/llvm/test/CodeGen/Thumb/
Duxth.ll12 define i32 @uxtb(i32 %x) {
13 ; V6M-LABEL: uxtb:
14 ; V6M: uxtb r0, r0
34 ; V6M: uxtb r1, r1
35 ; V6M-NEXT: uxtb r0, r0
133 ; V6M-NEXT: uxtb r3, r2
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
Dextended-register.s10 sub w12, w13, w14, uxtb #0
53 # EM3-NEXT: 1 1 0.25 sub w12, w13, w14, uxtb
62 # EM4-NEXT: 1 1 0.25 sub w12, w13, w14, uxtb
71 # EM5-NEXT: 1 1 0.17 sub w12, w13, w14, uxtb
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s170 add w1, w2, w3, uxtb
179 ; CHECK: add w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x0b]
188 add x1, x2, w3, uxtb
195 ; CHECK: add x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x8b]
214 sub w1, w2, w3, uxtb
223 ; CHECK: sub w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x4b]
232 sub x1, x2, w3, uxtb
239 ; CHECK: sub x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xcb]
258 adds w1, w2, w3, uxtb
267 ; CHECK: adds w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x2b]
[all …]
/external/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s170 add w1, w2, w3, uxtb
179 ; CHECK: add w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x0b]
188 add x1, x2, w3, uxtb
195 ; CHECK: add x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x8b]
214 sub w1, w2, w3, uxtb
223 ; CHECK: sub w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x4b]
232 sub x1, x2, w3, uxtb
239 ; CHECK: sub x1, x2, w3, uxtb ; encoding: [0x41,0x00,0x23,0xcb]
258 adds w1, w2, w3, uxtb
267 ; CHECK: adds w1, w2, w3, uxtb ; encoding: [0x41,0x00,0x23,0x2b]
[all …]
/external/llvm/test/CodeGen/AArch64/
Daddsub_ext.ll22 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
27 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
34 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
39 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
67 ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, uxtb
97 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb
102 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, uxtb #3
109 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb
114 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, uxtb #1
/external/llvm/test/MC/ARM/
Dthumb.s33 uxtb r3, r6
35 @ CHECK: uxtb r3, r6 @ encoding: [0xf3,0xb2]
/external/llvm-project/llvm/test/MC/ARM/
Dthumb.s33 uxtb r3, r6
35 @ CHECK: uxtb r3, r6 @ encoding: [0xf3,0xb2]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dthumb2-shifter.ll43 ; A8: uxtb r2, r2
58 ; A8: uxtb r2, r2
73 ; A8: uxtb r2, r2
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-shifter.ll43 ; A8: uxtb r2, r2
58 ; A8: uxtb r2, r2
73 ; A8: uxtb r2, r2
/external/llvm-project/libc/AOR_v20.02/string/arm/
Dstrcmp.S282 uxtb tmp1, data1, ror #BYTE1_OFFSET
289 uxtb tmp1, data1, ror #BYTE2_OFFSET
296 uxtb tmp1, data1, ror #BYTE3_OFFSET
305 uxtb tmp1, data1, ror #BYTE2_OFFSET
312 uxtb tmp1, data1, ror #BYTE3_OFFSET
Dstrcmp-armv6m.S59 uxtb r0, r2
60 uxtb r1, r3
/external/arm-optimized-routines/string/arm/
Dstrcmp.S280 uxtb tmp1, data1, ror #BYTE1_OFFSET
287 uxtb tmp1, data1, ror #BYTE2_OFFSET
294 uxtb tmp1, data1, ror #BYTE3_OFFSET
303 uxtb tmp1, data1, ror #BYTE2_OFFSET
310 uxtb tmp1, data1, ror #BYTE3_OFFSET
Dstrcmp-armv6m.S58 uxtb r0, r2
59 uxtb r1, r3

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