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Searched refs:v16i32 (Results 1 – 25 of 253) sorted by relevance

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/external/llvm-project/llvm/lib/Target/X86/
DX86InstrVecCompiler.td82 defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>;
93 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
131 defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32, sub_xmm>;
132 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32, sub_xmm>;
133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
134 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32, sub_xmm>;
135 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32, sub_xmm>;
136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>;
138 defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32, sub_ymm>;
139 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>;
[all …]
DX86TargetTransformInfo.cpp325 { ISD::SDIV, MVT::v16i32, 6 }, // pmuludq sequence in getArithmeticInstrCost()
326 { ISD::SREM, MVT::v16i32, 8 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
327 { ISD::UDIV, MVT::v16i32, 5 }, // pmuludq sequence in getArithmeticInstrCost()
328 { ISD::UREM, MVT::v16i32, 7 }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
405 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
406 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
407 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
408 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
578 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
579 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td82 defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>;
93 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
131 defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32, sub_xmm>;
132 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32, sub_xmm>;
133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
134 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32, sub_xmm>;
135 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32, sub_xmm>;
136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>;
138 defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32, sub_ymm>;
139 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>;
[all …]
DX86TargetTransformInfo.cpp369 { ISD::SDIV, MVT::v16i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
371 { ISD::UDIV, MVT::v16i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
372 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence in getArithmeticInstrCost()
525 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
526 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
527 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
538 { ISD::MUL, MVT::v16i32, 1 }, // pmulld (Skylake from agner.org) in getArithmeticInstrCost()
1036 {TTI::SK_Broadcast, MVT::v16i32, 1}, // vpbroadcastd in getShuffleCost()
1041 {TTI::SK_Reverse, MVT::v16i32, 1}, // vpermd in getShuffleCost()
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dintrinsic-cost-kinds.ll14 declare {<16 x i32>, <16 x i1>} @llvm.umul.with.overflow.v16i32(<16 x i32>, <16 x i32>)
17 declare <16 x i32> @llvm.smax.v16i32(<16 x i32>, <16 x i32>)
32 declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>, i1)
35 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1)
38 declare <16 x i32> @llvm.fshl.v16i32(<16 x i32>, <16 x i32>, <16 x i32>)
51 …nstruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <1…
56 …nstruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <1…
61 …nstruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <1…
66 …nstruction: %v = call { <16 x i32>, <16 x i1> } @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <1…
70 %v = call {<16 x i32>, <16 x i1>} @llvm.umul.with.overflow.v16i32(<16 x i32> %va, <16 x i32> %vb)
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-64b.ll25 %t0 = call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %a0)
52 %t0 = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a0)
108 %t0 = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %a0)
115 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>) #0
119 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>) #0
123 declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>) #0
Dbswap.ll17 %v0 = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %a0)
40 declare <16 x i32> @llvm.bswap.v16i32(<16 x i32>) #0
Disel-widen-truncate-pair.ll3 ; This has a v32i8 = truncate v16i32 (64b mode), which was legalized to
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dintrinsic-cost-kinds.ll14 declare <16 x i32> @llvm.smax.v16i32(<16 x i32>, <16 x i32>)
29 declare <16 x i32> @llvm.cttz.v16i32(<16 x i32>, i1)
32 declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>, i1)
35 declare <16 x i32> @llvm.fshl.v16i32(<16 x i32>, <16 x i32>, <16 x i32>)
46 …an estimated cost of 16 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <1…
51 … an estimated cost of 1 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <1…
56 … an estimated cost of 2 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <1…
61 … an estimated cost of 4 for instruction: %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <1…
65 %v = call <16 x i32> @llvm.smax.v16i32(<16 x i32> %va, <16 x i32> %vb)
176 …n estimated cost of 528 for instruction: %v = call <16 x i32> @llvm.cttz.v16i32(<16 x i32> %va, i1…
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-minmaxv.ll145 declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32>)
154 %r = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %arr.load)
169 declare i32 @llvm.vector.reduce.umin.v16i32(<16 x i32>)
178 %r = call i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %arr.load)
193 declare i32 @llvm.vector.reduce.smax.v16i32(<16 x i32>)
202 %r = call i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %arr.load)
217 declare i32 @llvm.vector.reduce.smin.v16i32(<16 x i32>)
226 %r = call i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %arr.load)
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
558 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 }, in getCastInstrCost()
559 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 }, in getCastInstrCost()
564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 }, in getCastInstrCost()
566 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
567 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }, in getCastInstrCost()
568 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i16, 1 }, in getCastInstrCost()
[all …]
DX86CallingConv.td68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
122 CCIfType<[v16f32, v8f64, v16i32, v8i64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
366 CCIfType<[v16i32, v8i64, v16f32, v8f64],
406 CCIfType<[v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dscatter-schedule.ll19 …call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %x270, <16 x i32*> %x335, i32 4, <16 x i…
22 declare void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> , <16 x i32*> , i32, <16 x i1> )
Davx512vpopcntdq-intrinsics.ll23 %1 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %b)
41 %1 = tail call <16 x i32> @llvm.ctpop.v16i32(<16 x i32> %a)
87 declare <16 x i32> @llvm.ctpop.v16i32(<16 x i32>)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h91 v16i32 = 42, // 16 x i32 enumerator
266 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 || in is512BitVector()
346 case v16i32: in getVectorElementType()
392 case v16i32: in getVectorNumElements()
499 case v16i32: in getSizeInBits()
628 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td85 CCIfType<[v16i32,v32i16,v64i8],
91 CCIfType<[v16i32,v32i16,v64i8],
117 CCIfType<[v16i32,v32i16,v64i8],
DHexagonIntrinsics.td263 def : Pat <(v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
264 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo))>,
267 def : Pat <(v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
268 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi))>,
280 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
281 (v512i1 (V6_vandvrt (v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
292 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
293 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
331 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101))))>,
336 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
28 def : Pat <(v512i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v512i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
37 def : Pat <(v16i32 (bitconvert (v512i1 HvxQR:$src1))),
38 (v16i32 (V6_vandqrt(v512i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
67 (v16i32 (V6_vandqrt (v512i1 HvxQR:$src1),
72 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td115 CCIfType<[v16i32,v32i16,v64i8],
121 CCIfType<[v16i32,v32i16,v64i8],
147 CCIfType<[v16i32,v32i16,v64i8],
DHexagonIntrinsicsV60.td15 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 HvxWR:$src1))),
16 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_lo)) >;
18 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 HvxWR:$src1))),
19 (v16i32 (EXTRACT_SUBREG (v32i32 HvxWR:$src1), vsub_hi)) >;
28 def : Pat <(v64i1 (bitconvert (v16i32 HvxVR:$src1))),
29 (v64i1 (V6_vandvrt(v16i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
37 def : Pat <(v16i32 (bitconvert (v64i1 HvxQR:$src1))),
38 (v16i32 (V6_vandqrt(v64i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
67 (v16i32 (V6_vandqrt (v64i1 HvxQR:$src1),
72 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-load.mir21 %global.not.uniform.v16i32 = getelementptr <16 x i32>, <16 x i32> addrspace(1)* %in, i32 %tmp0
22 %tmp2 = load <16 x i32>, <16 x i32> addrspace(1)* %global.not.uniform.v16i32
64 %constant.not.uniform.v16i32 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %in, i32 %tmp0
65 %tmp2 = load <16 x i32>, <16 x i32> addrspace(4)* %constant.not.uniform.v16i32
158 …<4 x s32>) = G_LOAD [[COPY]](p1) :: (load 16 from %ir.global.not.uniform.v16i32, align 64, addrspa…
161 …x s32>) = G_LOAD [[PTR_ADD]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 16, align 64, ad…
164 … s32>) = G_LOAD [[PTR_ADD1]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 32, align 64, ad…
167 … s32>) = G_LOAD [[PTR_ADD2]](p1) :: (load 16 from %ir.global.not.uniform.v16i32 + 48, align 64, ad…
170 %1:_(<16 x s32>) = G_LOAD %0 :: (load 64 from %ir.global.not.uniform.v16i32)
339 … x s32>) = G_LOAD [[COPY]](p4) :: (load 16 from %ir.constant.not.uniform.v16i32, align 64, addrspa…
[all …]
/external/llvm-project/llvm/test/Transforms/LoopVectorize/X86/
Dgather_scatter.ll35 ; AVX512-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 …
50 ; AVX512-NEXT: [[WIDE_MASKED_LOAD_1:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<1…
65 ; AVX512-NEXT: [[WIDE_MASKED_LOAD_2:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<1…
80 ; AVX512-NEXT: [[WIDE_MASKED_LOAD_3:%.*]] = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<1…
208 ; AVX512-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(…
216 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_1:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
224 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_2:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
232 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_3:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
240 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_4:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
248 ; AVX512-NEXT: [[WIDE_MASKED_GATHER_5:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i3…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h98 v16i32 = 49, // 16 x i32 enumerator
370 SimpleTy == MVT::v16i32 || SimpleTy == MVT::v8i64); in is512BitVector()
481 case v16i32: in getVectorElementType()
588 case v16i32: in getVectorNumElements()
793 case v16i32: in getSizeInBits()
964 if (NumElements == 16) return MVT::v16i32; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dv6vec_zero.ll5 ; generating a v16i32 constant pool node.
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td65 def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
66 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_loreg)) >,
69 def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
70 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), subreg_hireg)) >,
84 def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
85 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
104 def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
105 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
167 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
173 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,

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