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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME_P9.txt101 (set v1i128:$rD, (int_ppc_altivec_vprtybq v1i128:$vB))
134 VX1_Int_Ty<513, "vmul10uq", int_ppc_altivec_vmul10uq, v1i128>;
135 VX1_Int_Ty< 1, "vmul10cuq", int_ppc_altivec_vmul10cuq, v1i128>;
140 VX1_Int_Ty<577, "vmul10euq", int_ppc_altivec_vmul10euq, v1i128>;
141 VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
146 (set v1i128:$vD, (int_ppc_altivec_bcdcfno v1i128:$vB, i1:$PS))
147 (set v1i128:$vD, (int_ppc_altivec_bcdcfzo v1i128:$vB, i1:$PS))
148 (set v1i128:$vD, (int_ppc_altivec_bcdctno v1i128:$vB))
149 (set v1i128:$vD, (int_ppc_altivec_bcdctzo v1i128:$vB, i1:$PS))
150 (set v1i128:$vD, (int_ppc_altivec_bcdcfsqo v1i128:$vB, i1:$PS))
[all …]
DPPCInstrAltivec.td884 def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;
890 def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>;
896 def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>;
902 def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>;
908 def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>;
910 def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>;
911 def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>;
912 def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>;
913 def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>;
914 def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>;
[all …]
DPPCCallingConv.td67 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
107 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
163 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
251 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
/external/llvm/lib/Target/PowerPC/
DREADME_P9.txt101 (set v1i128:$rD, (int_ppc_altivec_vprtybq v1i128:$vB))
134 VX1_Int_Ty<513, "vmul10uq", int_ppc_altivec_vmul10uq, v1i128>;
135 VX1_Int_Ty< 1, "vmul10cuq", int_ppc_altivec_vmul10cuq, v1i128>;
140 VX1_Int_Ty<577, "vmul10euq", int_ppc_altivec_vmul10euq, v1i128>;
141 VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
146 (set v1i128:$vD, (int_ppc_altivec_bcdcfno v1i128:$vB, i1:$PS))
147 (set v1i128:$vD, (int_ppc_altivec_bcdcfzo v1i128:$vB, i1:$PS))
148 (set v1i128:$vD, (int_ppc_altivec_bcdctno v1i128:$vB))
149 (set v1i128:$vD, (int_ppc_altivec_bcdctzo v1i128:$vB, i1:$PS))
150 (set v1i128:$vD, (int_ppc_altivec_bcdcfsqo v1i128:$vB, i1:$PS))
[all …]
DPPCInstrAltivec.td859 def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;
865 def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>;
871 def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>;
877 def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>;
883 def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>;
885 def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>;
886 def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>;
887 def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>;
888 def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>;
889 def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>;
[all …]
DPPCCallingConv.td68 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
121 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
190 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32],
/external/llvm-project/llvm/lib/Target/PowerPC/
DREADME_P9.txt101 (set v1i128:$rD, (int_ppc_altivec_vprtybq v1i128:$vB))
134 VX1_Int_Ty<513, "vmul10uq", int_ppc_altivec_vmul10uq, v1i128>;
135 VX1_Int_Ty< 1, "vmul10cuq", int_ppc_altivec_vmul10cuq, v1i128>;
140 VX1_Int_Ty<577, "vmul10euq", int_ppc_altivec_vmul10euq, v1i128>;
141 VX1_Int_Ty< 65, "vmul10ecuq", int_ppc_altivec_vmul10ecuq, v1i128>;
146 (set v1i128:$vD, (int_ppc_altivec_bcdcfno v1i128:$vB, i1:$PS))
147 (set v1i128:$vD, (int_ppc_altivec_bcdcfzo v1i128:$vB, i1:$PS))
148 (set v1i128:$vD, (int_ppc_altivec_bcdctno v1i128:$vB))
149 (set v1i128:$vD, (int_ppc_altivec_bcdctzo v1i128:$vB, i1:$PS))
150 (set v1i128:$vD, (int_ppc_altivec_bcdcfsqo v1i128:$vB, i1:$PS))
[all …]
DPPCInstrPrefix.td51 SDTCisVT<0, v1i128>, SDTCisPtrTy<1>, SDTCisPtrTy<2>
2042 (int_ppc_altivec_vextractqm v1i128:$vB))]>;
2061 [(set v1i128:$vD, (int_ppc_altivec_vexpandqm
2062 v1i128:$vB))]>;
2081 [(set v1i128:$vD,
2192 (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>;
2314 [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA,
2318 [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA,
2322 [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA,
2326 [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA,
[all …]
DPPCInstrAltivec.td904 def : Pat<(v16i8 (bitconvert (v1i128 VRRC:$src))), (v16i8 VRRC:$src)>;
910 def : Pat<(v8i16 (bitconvert (v1i128 VRRC:$src))), (v8i16 VRRC:$src)>;
916 def : Pat<(v4i32 (bitconvert (v1i128 VRRC:$src))), (v4i32 VRRC:$src)>;
922 def : Pat<(v4f32 (bitconvert (v1i128 VRRC:$src))), (v4f32 VRRC:$src)>;
928 def : Pat<(v2i64 (bitconvert (v1i128 VRRC:$src))), (v2i64 VRRC:$src)>;
930 def : Pat<(v1i128 (bitconvert (v16i8 VRRC:$src))), (v1i128 VRRC:$src)>;
931 def : Pat<(v1i128 (bitconvert (v8i16 VRRC:$src))), (v1i128 VRRC:$src)>;
932 def : Pat<(v1i128 (bitconvert (v4i32 VRRC:$src))), (v1i128 VRRC:$src)>;
933 def : Pat<(v1i128 (bitconvert (v4f32 VRRC:$src))), (v1i128 VRRC:$src)>;
934 def : Pat<(v1i128 (bitconvert (v2i64 VRRC:$src))), (v1i128 VRRC:$src)>;
[all …]
DPPCCallingConv.td64 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
100 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
154 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
235 CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64],
DPPCISelLowering.cpp733 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
743 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
856 setOperationAction(ISD::ROTL, MVT::v1i128, Custom); in PPCTargetLowering()
897 setOperationAction(ISD::UREM, MVT::v1i128, Legal); in PPCTargetLowering()
898 setOperationAction(ISD::SREM, MVT::v1i128, Legal); in PPCTargetLowering()
899 setOperationAction(ISD::UDIV, MVT::v1i128, Legal); in PPCTargetLowering()
900 setOperationAction(ISD::SDIV, MVT::v1i128, Legal); in PPCTargetLowering()
901 setOperationAction(ISD::ROTL, MVT::v1i128, Legal); in PPCTargetLowering()
997 setOperationAction(ISD::SHL, MVT::v1i128, Expand); in PPCTargetLowering()
998 setOperationAction(ISD::SRL, MVT::v1i128, Expand); in PPCTargetLowering()
[all …]
/external/llvm-project/clang/test/CodeGen/RISCV/
Driscv64-lp64-lp64f-lp64d-abi.c117 typedef __int128_t v1i128 __attribute__((vector_size(16))); typedef
130 void f_vec_small_v1i128(v1i128 x) { in f_vec_small_v1i128()
135 v1i128 f_vec_small_v1i128_ret() { in f_vec_small_v1i128_ret()
136 return (v1i128){1}; in f_vec_small_v1i128_ret()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h102 v1i128 = 51, // 1 x i128 enumerator
105 LAST_INTEGER_VECTOR_VALUETYPE = v1i128,
251 SimpleTy == MVT::v1i128 || SimpleTy == MVT::v8f16 || in is128BitVector()
355 case v1i128: return i128; in getVectorElementType()
423 case v1i128: in getVectorNumElements()
486 case v1i128: in getSizeInBits()
641 if (NumElements == 1) return MVT::v1i128; in getVectorVT()
DValueTypes.td79 def v1i128 : ValueType<128, 51>; // 1 x i128 vector value
/external/clang/test/CodeGen/
Dsystemz-abi-vector.c31 typedef __attribute__((vector_size(16))) __int128 v1i128; typedef
102 v1i128 pass_v1i128(v1i128 arg) { return arg; } in pass_v1i128()
/external/llvm-project/clang/test/CodeGen/SystemZ/
Dsystemz-abi-vector.c41 typedef __attribute__((vector_size(16))) __int128 v1i128; typedef
112 v1i128 pass_v1i128(v1i128 arg) { return arg; } in pass_v1i128()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h114 v1i128 = 63, // 1 x i128 enumerator
117 LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
352 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 || in is128BitVector()
507 case v1i128: return i128; in getVectorElementType()
657 case v1i128: in getVectorNumElements()
763 case v1i128: in getSizeInBits()
982 if (NumElements == 1) return MVT::v1i128; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h118 v1i128 = 67, // 1 x i128 enumerator
121 LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
383 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 || in is128BitVector()
579 case v1i128: return i128; in getVectorElementType()
775 case v1i128: in getVectorNumElements()
895 case v1i128: in getSizeInBits()
1172 if (NumElements == 1) return MVT::v1i128; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvec-bswap.ll99 %0 = call <1 x i128> @llvm.bswap.v1i128(<1 x i128> %a)
104 declare <1 x i128> @llvm.bswap.v1i128(<1 x i128>)
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dvecreduce-add-legalization.ll10 declare i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)
81 %b = call i128 @llvm.vector.reduce.add.v1i128(<1 x i128> %a)
Dvecreduce-umax-legalization.ll10 declare i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)
82 %b = call i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)
Dvecreduce-and-legalization.ll10 declare i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
81 %b = call i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
/external/llvm/lib/IR/
DValueTypes.cpp183 case MVT::v1i128: return "v1i128"; in getEVTString()
261 case MVT::v1i128: return VectorType::get(Type::getInt128Ty(Context), 1); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenCallingConv.inc63 LocVT == MVT::v1i128 ||
520 LocVT == MVT::v1i128 ||
668 LocVT == MVT::v1i128 ||
774 LocVT == MVT::v1i128 ||
DPPCGenDAGISel.inc17428 MVT::v1i128, 3/*#Ops*/, 0, 1, 2,
17429 … (intrinsic_wo_chain:{ *:[v1i128] } 5637:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i1…
17430 …// Dst: (VADDEUQM:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:…
17437 MVT::v1i128, 2/*#Ops*/, 0, 1,
17438 …// Src: (intrinsic_wo_chain:{ *:[v1i128] } 5634:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ …
17439 … // Dst: (VADDCUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB)
17447 MVT::v1i128, 3/*#Ops*/, 0, 1, 2,
17448 … (intrinsic_wo_chain:{ *:[v1i128] } 5636:{ *:[iPTR] }, v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i1…
17449 …// Dst: (VADDECUQ:{ *:[v1i128] } v1i128:{ *:[v1i128] }:$vA, v1i128:{ *:[v1i128] }:$vB, v1i128:{ *:…
17457 MVT::v1i128, 3/*#Ops*/, 0, 1, 2,
[all …]

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