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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.buffer.store.dwordx3.ll8 …call void @llvm.amdgcn.buffer.store.format.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0…
17 call void @llvm.amdgcn.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
26 …call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, …
35 call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 42, i32 0, i32 0)
44 …call void @llvm.amdgcn.struct.buffer.store.v3f32(<3 x float> %1, <4 x i32> %0, i32 0, i32 42, i32 …
48 declare void @llvm.amdgcn.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i1, i1) #0
49 declare void @llvm.amdgcn.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i1, i1) #0
50 declare void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #0
51 declare void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float>, <4 x i32>, i32, i32, i32) #0
52 declare void @llvm.amdgcn.struct.buffer.store.format.v3f32(<3 x float>, <4 x i32>, i32, i32, i32, i…
[all …]
Dllvm.amdgcn.buffer.load.dwordx3.ll10 …%data = call <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42, i1 0, …
20 %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i1 0, i1 0)
30 %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %0, i32 40, i32 0, i32 0)
40 …%data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %0, i32 0, i32 42,…
50 …%data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %0, i32 0, i32 40, i32 0,…
54 declare <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32>, i32, i32, i1, i1) #0
55 declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #0
56 declare <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32) #0
57 declare <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32>, i32, i32, i32) #0
58 declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32) #0
[all …]
Drewrite-out-arguments.ll31 ; CHECK: %bitcast_struct_v3f32_v3f32 = type { %struct.v3f32 }
32 ; CHECK: %struct.v3f32 = type { <3 x float> }
33 ; CHECK: %bitcast_struct_v3f32_v3i32 = type { %struct.v3f32 }
36 ; CHECK: %bitcast_struct_v3f32_v4i32 = type { %struct.v3f32 }
38 ; CHECK: %struct.v3f32.f32 = type { <3 x float>, float }
41 ; CHECK: %multi_return_bitcast_struct_v3f32_v3f32 = type { %struct.v3f32 }
643 %struct.v3f32 = type { <3 x float> }
644 %struct.v3f32.f32 = type { <3 x float>, float }
647 …vate %bitcast_struct_v3f32_v3f32 @bitcast_struct_v3f32_v3f32.body(%struct.v3f32* %out, <3 x float>…
649 ; CHECK-NEXT: %cast = bitcast %struct.v3f32* %out to <4 x float>*
[all …]
Dllvm.amdgcn.image.load.a16.ll24 ; GCN-LABEL: {{^}}load.v3f32.1d:
27 define amdgpu_ps <4 x float> @load.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
66 ; GCN-LABEL: {{^}}load.v3f32.2d:
69 define amdgpu_ps <4 x float> @load.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
112 ; GCN-LABEL: {{^}}load.v3f32.3d:
115 define amdgpu_ps <4 x float> @load.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> …
Dmad-mix-lo.ll106 …%result = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, …
159 …%result = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, …
260 …%result = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %src0.ext, <3 x float> %src1.ext, …
261 %max = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %result, <3 x float> zeroinitializer)
262 …%clamp = call <3 x float> @llvm.minnum.v3f32(<3 x float> %max, <3 x float> <float 1.0, float 1.0, …
300 declare <3 x float> @llvm.minnum.v3f32(<3 x float>, <3 x float>) #1
305 declare <3 x float> @llvm.maxnum.v3f32(<3 x float>, <3 x float>) #1
310 declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) #1
Dftrunc.ll7 declare <3 x float> @llvm.trunc.v3f32(<3 x float>) nounwind readnone
40 ; %y = call <3 x float> @llvm.trunc.v3f32(<3 x float> %x) nounwind readnone
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dvec-libcalls.ll10 declare <3 x float> @llvm.sin.v3f32(<3 x float>)
20 declare <3 x float> @llvm.fabs.v3f32(<3 x float>)
21 declare <3 x float> @llvm.ceil.v3f32(<3 x float>)
22 declare <3 x float> @llvm.cos.v3f32(<3 x float>)
23 declare <3 x float> @llvm.exp.v3f32(<3 x float>)
24 declare <3 x float> @llvm.exp2.v3f32(<3 x float>)
25 declare <3 x float> @llvm.floor.v3f32(<3 x float>)
26 declare <3 x float> @llvm.log.v3f32(<3 x float>)
27 declare <3 x float> @llvm.log10.v3f32(<3 x float>)
28 declare <3 x float> @llvm.log2.v3f32(<3 x float>)
[all …]
Dvecreduce-fmin-legalization.ll9 declare float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
55 %b = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
67 %b = call nnan ninf float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a)
Dvecreduce-fmax-legalization.ll9 declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
55 %b = call nnan float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
67 %b = call nnan ninf float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
Dvecreduce-fmax-legalization-nan.ll9 declare float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
50 ; %b = call float @llvm.vector.reduce.fmax.v3f32(<3 x float> %a)
Dvecreduce-fmul-legalization-strict.ll11 declare float @llvm.vector.reduce.fmul.f32.v3f32(float, <3 x float>)
55 %b = call float @llvm.vector.reduce.fmul.f32.v3f32(float 1.0, <3 x float> %a)
/external/llvm/test/CodeGen/X86/
Dextended-fma-contraction.ll18 %ret = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %a, <3 x float> %b, <3 x float> %c)
22 declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) nounwind readnone
/external/clang/test/CodeGen/
Dvectorcall.c72 typedef float __attribute__((ext_vector_type(3))) v3f32; typedef
73 struct OddSizeHVA { v3f32 x, y; };
/external/llvm-project/llvm/test/CodeGen/X86/
Dextended-fma-contraction.ll16 %ret = tail call <3 x float> @llvm.fmuladd.v3f32(<3 x float> %a, <3 x float> %b, <3 x float> %c)
20 declare <3 x float> @llvm.fmuladd.v3f32(<3 x float>, <3 x float>, <3 x float>) nounwind readnone
Dvector-constrained-fp-intrinsics-flags.ll29 %add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32(
60 declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, m…
/external/llvm-project/clang/test/CodeGen/
Dregcall.c106 typedef float __attribute__((ext_vector_type(3))) v3f32; typedef
107 struct OddSizeHVA { v3f32 x, y; };
Dvectorcall.c96 typedef float __attribute__((ext_vector_type(3))) v3f32; typedef
97 struct OddSizeHVA { v3f32 x, y; };
/external/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
Dfma.ll29 ; SLOWF32: estimated cost of 12 for {{.*}} call <3 x float> @llvm.fma.v3f32
30 ; FASTF32: estimated cost of 6 for {{.*}} call <3 x float> @llvm.fma.v3f32
31 ; SIZEALL: estimated cost of 6 for {{.*}} call <3 x float> @llvm.fma.v3f32
34 %fma = call <3 x float> @llvm.fma.v3f32(<3 x float> %vec, <3 x float> %vec, <3 x float> %vec) #1
120 declare <3 x float> @llvm.fma.v3f32(<3 x float>, <3 x float>, <3 x float>) #1
Dfabs.ll23 ; CHECK: estimated cost of 0 for {{.*}} call <3 x float> @llvm.fabs.v3f32
26 %fabs = call <3 x float> @llvm.fabs.v3f32(<3 x float> %vec) #1
96 declare <3 x float> @llvm.fabs.v3f32(<3 x float>) #1
/external/llvm/test/Analysis/CostModel/AMDGPU/
Dfabs.ll22 ; CHECK: estimated cost of 0 for {{.*}} call <3 x float> @llvm.fabs.v3f32
25 %fabs = call <3 x float> @llvm.fabs.v3f32(<3 x float> %vec) #1
86 declare <3 x float> @llvm.fabs.v3f32(<3 x float>) #1
/external/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/
Damdgcn-demanded-vector-elts.ll78 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
107 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
127 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
172 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
192 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
208 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
225 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
243 …%data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 fa…
253 …%data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 fa…
259 ; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i3…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.wwm.ll72 %ret = call <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float> %val)
79 declare <3 x float> @llvm.amdgcn.wwm.v3f32(<3 x float>) #0
Dllvm.amdgcn.wqm.ll72 %ret = call <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float> %val)
79 declare <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float>) #0
Dllvm.amdgcn.softwqm.ll72 %ret = call <3 x float> @llvm.amdgcn.softwqm.v3f32(<3 x float> %val)
79 declare <3 x float> @llvm.amdgcn.softwqm.v3f32(<3 x float>) #0
/external/llvm/test/CodeGen/AMDGPU/
Dftrunc.ll7 declare <3 x float> @llvm.trunc.v3f32(<3 x float>) nounwind readnone
40 ; %y = call <3 x float> @llvm.trunc.v3f32(<3 x float> %x) nounwind readnone

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