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Searched refs:v64i16 (Results 1 – 25 of 70) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td88 CCIfType<[v32i32,v64i16,v128i8],
94 CCIfType<[v32i32,v64i16,v128i8],
99 CCIfType<[v32i32,v64i16,v128i8],
105 CCIfType<[v32i32,v64i16,v128i8],
120 CCIfType<[v32i32,v64i16,v128i8],
125 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsics.td308 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
309 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
320 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
321 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
350 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
351 (v64i16 (V6_vpackwh_sat
DHexagonIntrinsicsV60.td49 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
50 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
58 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
59 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
635 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
636 (v64i16 (V6_vpackwh_sat
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td118 CCIfType<[v32i32,v64i16,v128i8],
124 CCIfType<[v32i32,v64i16,v128i8],
129 CCIfType<[v32i32,v64i16,v128i8],
135 CCIfType<[v32i32,v64i16,v128i8],
150 CCIfType<[v32i32,v64i16,v128i8],
155 CCIfType<[v32i32,v64i16,v128i8],
DHexagonIntrinsicsV60.td49 def : Pat <(v128i1 (bitconvert (v64i16 HvxVR:$src1))),
50 (v128i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
58 def : Pat <(v64i16 (bitconvert (v128i1 HvxQR:$src1))),
59 (v64i16 (V6_vandqrt (v128i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
635 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
636 (v64i16 (V6_vpackwh_sat
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-128b.ll16 %t0 = call <64 x i16> @llvm.ctpop.v64i16(<64 x i16> %a0)
45 %t0 = call <64 x i16> @llvm.ctlz.v64i16(<64 x i16> %a0)
92 %t0 = call <64 x i16> @llvm.cttz.v64i16(<64 x i16> %a0)
113 declare <64 x i16> @llvm.ctpop.v64i16(<64 x i16>) #0
117 declare <64 x i16> @llvm.ctlz.v64i16(<64 x i16>) #0
121 declare <64 x i16> @llvm.cttz.v64i16(<64 x i16>) #0
Dbswap.ll26 %v0 = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %a0)
41 declare <64 x i16> @llvm.bswap.v64i16(<64 x i16>) #1
Disel-split-masked.ll20 …call void @llvm.masked.store.v64i16.p0v64i16(<64 x i16> %v8, <64 x i16>* undef, i32 2, <64 x i1> <…
28 declare void @llvm.masked.store.v64i16.p0v64i16(<64 x i16>, <64 x i16>*, i32 immarg, <64 x i1>) #2
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h84 v64i16 = 36, // 64 x i16 enumerator
273 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
340 case v64i16: in getVectorElementType()
382 case v64i16: in getVectorNumElements()
505 case v64i16: in getSizeInBits()
620 if (NumElements == 64) return MVT::v64i16; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h89 v64i16 = 41, // 64 x i16 enumerator
376 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
467 case v64i16: in getVectorElementType()
570 case v64i16: in getVectorNumElements()
805 case v64i16: in getSizeInBits()
954 if (NumElements == 64) return MVT::v64i16; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/X86/
Davx512bw-intrinsics-canonical.ll256 %1 = call <64 x i16> @llvm.sadd.sat.v64i16(<64 x i16> %a, <64 x i16> %b)
259 declare <64 x i16> @llvm.sadd.sat.v64i16(<64 x i16>, <64 x i16>)
283 %sub = call <64 x i16> @llvm.ssub.sat.v64i16(<64 x i16> %a, <64 x i16> %b)
286 declare <64 x i16> @llvm.ssub.sat.v64i16(<64 x i16>, <64 x i16>);
537 %1 = call <64 x i16> @llvm.uadd.sat.v64i16(<64 x i16> %a, <64 x i16> %b)
540 declare <64 x i16> @llvm.uadd.sat.v64i16(<64 x i16>, <64 x i16>)
564 %sub = call <64 x i16> @llvm.usub.sat.v64i16(<64 x i16> %a, <64 x i16> %b)
567 declare <64 x i16> @llvm.usub.sat.v64i16(<64 x i16>, <64 x i16>)
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h90 v64i16 = 42, // 64 x i16 enumerator
409 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector()
536 case v64i16: in getVectorElementType()
669 case v64i16: in getVectorNumElements()
944 case v64i16: in getSizeInBits()
1141 if (NumElements == 64) return MVT::v64i16; in getVectorVT()
/external/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dbitconvert-vector.ll3 ; This testcase would fail on a bitcast from v64i16 to v32i32. Check that
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dreduce-umin.ll79 …ated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
88 …ated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
97 …ted cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
105 %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
167 declare i16 @llvm.vector.reduce.umin.v64i16(<64 x i16>)
Dreduce-smin.ll79 …ated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
88 …ated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
97 …ted cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
105 %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
167 declare i16 @llvm.vector.reduce.smin.v64i16(<64 x i16>)
Dreduce-umax.ll79 …ated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
88 …ated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
97 …ted cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
105 %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
167 declare i16 @llvm.vector.reduce.umax.v64i16(<64 x i16>)
Dreduce-smax.ll79 …ated cost of 379 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
88 …ated cost of 503 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
97 …ted cost of 8880 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
105 %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
167 declare i16 @llvm.vector.reduce.smax.v64i16(<64 x i16>)
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-add.ll118 …imated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
127 …imated cost of 17 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
136 …timated cost of 8 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
145 …imated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
154 …imated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
163 …imated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
172 …imated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
180 %V64 = call i16 @llvm.vector.reduce.add.v64i16(<64 x i16> undef)
282 declare i16 @llvm.vector.reduce.add.v64i16(<64 x i16>)
Dreduce-umin.ll141 …mated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
150 …mated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
159 …mated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
168 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
177 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
186 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
195 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
204 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
212 %V64 = call i16 @llvm.vector.reduce.umin.v64i16(<64 x i16> undef)
324 declare i16 @llvm.vector.reduce.umin.v64i16(<64 x i16>)
Dreduce-smax.ll141 …mated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
150 …mated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
159 …mated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
168 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
177 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
186 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
195 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
204 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
212 %V64 = call i16 @llvm.vector.reduce.smax.v64i16(<64 x i16> undef)
324 declare i16 @llvm.vector.reduce.smax.v64i16(<64 x i16>)
Dreduce-umax.ll141 …mated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
150 …mated cost of 37 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
159 …mated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
168 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
177 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
186 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
195 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
204 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
212 %V64 = call i16 @llvm.vector.reduce.umax.v64i16(<64 x i16> undef)
324 declare i16 @llvm.vector.reduce.umax.v64i16(<64 x i16>)
Dreduce-smin.ll141 …mated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
150 …mated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
159 …mated cost of 11 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
168 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
177 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
186 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
195 …imated cost of 9 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
204 …mated cost of 15 for instruction: %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
212 %V64 = call i16 @llvm.vector.reduce.smin.v64i16(<64 x i16> undef)
324 declare i16 @llvm.vector.reduce.smin.v64i16(<64 x i16>)
Dreduce-mul.ll132 …imated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
141 …imated cost of 21 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
150 …imated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
159 …imated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
168 …imated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
177 …imated cost of 13 for instruction: %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
185 %V64 = call i16 @llvm.vector.reduce.mul.v64i16(<64 x i16> undef)
277 declare i16 @llvm.vector.reduce.mul.v64i16(<64 x i16>)
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
149 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
150 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
832 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
833 (v64i16 (V6_vpackwh_sat_128B

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