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Searched refs:v64i8 (Results 1 – 25 of 164) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dbitcount-64b.ll9 %t0 = call <64 x i8> @llvm.ctpop.v64i8(<64 x i8> %a0)
38 %t0 = call <64 x i8> @llvm.ctlz.v64i8(<64 x i8> %a0)
74 %t0 = call <64 x i8> @llvm.cttz.v64i8(<64 x i8> %a0)
113 declare <64 x i8> @llvm.ctpop.v64i8(<64 x i8>) #0
117 declare <64 x i8> @llvm.ctlz.v64i8(<64 x i8>) #0
121 declare <64 x i8> @llvm.cttz.v64i8(<64 x i8>) #0
Dwiden-ext.ll30 ; v64i8 -> v64i16
42 ; v64i8 -> v64i32
Dwiden-trunc.ll33 ; v64i16 -> v64i8
47 ; v64i32 -> v64i8
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp304 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
305 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
321 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand. in getArithmeticInstrCost()
322 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand. in getArithmeticInstrCost()
323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
386 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
387 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
388 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
389 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td87 defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
98 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>;
143 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32, sub_ymm>;
152 defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, sub_xmm>;
159 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32, sub_ymm>;
DX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
545 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
563 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
583 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
630 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
695 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h74 v64i8 = 27, // 64 x i8 enumerator
265 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
331 case v64i8: in getVectorElementType()
381 case v64i8: in getVectorNumElements()
497 case v64i8: in getSizeInBits()
609 if (NumElements == 64) return MVT::v64i8; in getVectorVT()
/external/llvm-project/llvm/test/Transforms/SCCP/
Dvector-bitcast.ll36 declare <64 x i8> @llvm.abs.v64i8(<64 x i8>, i1 immarg)
43 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <64 x i8> @llvm.abs.v64i8(<64 x i8> [[TMP1]], i1 false)
58 %tmp2 = tail call <64 x i8> @llvm.abs.v64i8(<64 x i8> %tmp1, i1 false)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td85 CCIfType<[v16i32,v32i16,v64i8],
91 CCIfType<[v16i32,v32i16,v64i8],
117 CCIfType<[v16i32,v32i16,v64i8],
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td115 CCIfType<[v16i32,v32i16,v64i8],
121 CCIfType<[v16i32,v32i16,v64i8],
147 CCIfType<[v16i32,v32i16,v64i8],
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp291 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand. in getArithmeticInstrCost()
292 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand. in getArithmeticInstrCost()
293 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
350 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
352 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence in getArithmeticInstrCost()
353 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
510 { ISD::SHL, MVT::v64i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
511 { ISD::SRL, MVT::v64i8, 11 }, // vpblendvb sequence. in getArithmeticInstrCost()
512 { ISD::SRA, MVT::v64i8, 24 }, // vpblendvb sequence. in getArithmeticInstrCost()
[all …]
DX86InstrVecCompiler.td87 defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
98 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>;
143 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32, sub_ymm>;
152 defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, sub_xmm>;
159 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32, sub_ymm>;
DX86CallingConv.td120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
539 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
557 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
577 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
624 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
689 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h78 v64i8 = 31, // 64 x i8 enumerator
369 SimpleTy == MVT::v64i8 || SimpleTy == MVT::v32i16 || in is512BitVector()
451 case v64i8: in getVectorElementType()
569 case v64i8: in getVectorNumElements()
791 case v64i8: in getSizeInBits()
942 if (NumElements == 64) return MVT::v64i8; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dhvx-bitcast-v64i1.ll20 …%v6 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* nonnull undef, i32 1, <64 x i1> %v…
44 declare <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>*, i32 immarg, <64 x i1>, <64 x i8>) #1
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dreduce-add.ll55 …stimated cost of 190 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
65 …stimated cost of 682 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
75 …stimated cost of 190 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
85 …stimated cost of 681 for instruction: %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
94 %V64 = call i8 @llvm.vector.reduce.add.v64i8(<64 x i8> undef)
123 declare i8 @llvm.vector.reduce.add.v64i8(<64 x i8>)
Darith-usat.ll27 declare <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8>, <64 x i8>)
46 …mated cost of 320 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
65 …imated cost of 12 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
84 …imated cost of 24 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
103 …imated cost of 66 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
122 …timated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
141 …timated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
162 %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef)
185 declare <64 x i8> @llvm.usub.sat.v64i8(<64 x i8>, <64 x i8>)
204 …mated cost of 320 for instruction: %V64I8 = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> undef, <…
[all …]
Darith-ssat.ll27 declare <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8>, <64 x i8>)
46 …ated cost of 1152 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
65 …imated cost of 40 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
84 …imated cost of 80 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
103 …mated cost of 136 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
122 …imated cost of 22 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
141 …imated cost of 16 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
162 %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <64 x i8> undef)
185 declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>)
204 …ated cost of 1152 for instruction: %V64I8 = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> undef, <…
[all …]
/external/llvm/lib/Target/X86/
DX86CallingConv.td51 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
68 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
149 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
328 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
346 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
449 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
524 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
541 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
560 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
601 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Darith-uminmax.ll29 declare <64 x i8> @llvm.umax.v64i8(<64 x i8>, <64 x i8>)
48 …n estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
67 …n estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
86 …n estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
105 …n estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
124 …n estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
143 …n estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
162 …n estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
181 …n estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <…
202 %V64I8 = call <64 x i8> @llvm.umax.v64i8(<64 x i8> undef, <64 x i8> undef)
[all …]
Darith-sminmax.ll29 declare <64 x i8> @llvm.smax.v64i8(<64 x i8>, <64 x i8>)
48 … estimated cost of 16 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
67 … estimated cost of 16 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
86 …n estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
105 …n estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
124 …n estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
143 …n estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
162 …n estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
181 …n estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <…
202 %V64I8 = call <64 x i8> @llvm.smax.v64i8(<64 x i8> undef, <64 x i8> undef)
[all …]
Darith-usat.ll36 declare <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8>, <64 x i8>)
55 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
74 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
93 …timated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
112 …timated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
131 …timated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
150 …timated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
169 …timated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
188 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
207 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> undef, <…
[all …]
Darith-ssat.ll35 declare <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8>, <64 x i8>)
54 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
73 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
92 …timated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
111 …timated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
130 …timated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
149 …timated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
168 …timated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
187 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
206 …timated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> undef, <…
[all …]
Dabs.ll184 …an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
191 …an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
198 …an estimated cost of 4 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
205 …an estimated cost of 6 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
212 …an estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
219 …an estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
226 …an estimated cost of 2 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
233 …an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
239 %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i1 0)
416 …an estimated cost of 8 for instruction: %V64I8 = call <64 x i8> @llvm.abs.v64i8(<64 x i8> %a512, i…
[all …]
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h79 v64i8 = 32, // 64 x i8 enumerator
401 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 || in is512BitVector()
519 case v64i8: in getVectorElementType()
668 case v64i8: in getVectorNumElements()
927 case v64i8: in getSizeInBits()
1129 if (NumElements == 64) return MVT::v64i8; in getVectorVT()

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