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/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dscalar-cmp-cmp-log-sel.ll8 i8 %val5, i8 %val6) {
12 %sel = select i1 %and, i8 %val5, i8 %val6
19 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i8 %val5, i8 %val6
23 i16 %val5, i16 %val6) {
27 %sel = select i1 %and, i16 %val5, i16 %val6
34 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i16 %val5, i16 %val6
38 i32 %val5, i32 %val6) {
42 %sel = select i1 %and, i32 %val5, i32 %val6
49 ; CHECK: cost of 1 for instruction: %sel = select i1 %and, i32 %val5, i32 %val6
53 i64 %val5, i64 %val6) {
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-cmp-cmp-logic-select.ll8 …0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i8> %val5, <2 x i8> %val6) {
19 %sel = select <2 x i1> %and, <2 x i8> %val5, <2 x i8> %val6
23 …<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4, <2 x i16> %val5, <2 x i16> %val6) {
35 %sel = select <2 x i1> %and, <2 x i16> %val5, <2 x i16> %val6
39 …i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i8> %val5, <16 x i8> %val6) {
52 %sel = select <16 x i1> %and, <16 x i8> %val5, <16 x i8> %val6
56 …> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4, <16 x i16> %val5, <16 x i16> %val6) {
75 %sel = select <16 x i1> %and, <16 x i16> %val5, <16 x i16> %val6
79 …x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4, <32 x i8> %val5, <32 x i8> %val6) {
98 %sel = select <32 x i1> %and, <32 x i8> %val5, <32 x i8> %val6
[all …]
Dspill-01.ll52 %val5 = load i32, i32 *%ptr5
62 store i32 %val5, i32 *%ptr5
90 %val5 = load i32, i32 *%ptr5
102 store i32 %val5, i32 *%ptr5
132 %val5 = load i64, i64 *%ptr5
144 store i64 %val5, i64 *%ptr5
178 %val5 = load float, float *%ptr5
191 store float %val5, float *%ptr5
222 %val5 = load double, double *%ptr5
235 store double %val5, double *%ptr5
[all …]
Dcond-move-10.ll31 %val5 = load i64, i64 *%ptr5
44 %add5 = add i64 %add4, %val5
77 %val5 = load i32, i32 *%ptr5
90 %add5 = add i32 %add4, %val5
/external/llvm-project/polly/test/ForwardOpTree/
Dforward_reusue.ll19 %val5 = fadd double %val4, %val4
23 store double %val5, double* %A
52 ; CHECK-NEXT: %val5 = fadd double %val4, %val4
62 ; CHECK-NEXT: %val5 = fadd double %val4, %val4
63 ; CHECK-NEXT: store double %val5, double* %A, align 8
/external/llvm/test/CodeGen/SystemZ/
Dspill-01.ll52 %val5 = load i32 , i32 *%ptr5
62 store i32 %val5, i32 *%ptr5
90 %val5 = load i32 , i32 *%ptr5
102 store i32 %val5, i32 *%ptr5
132 %val5 = load i64 , i64 *%ptr5
144 store i64 %val5, i64 *%ptr5
178 %val5 = load float , float *%ptr5
191 store float %val5, float *%ptr5
222 %val5 = load double , double *%ptr5
235 store double %val5, double *%ptr5
[all …]
/external/llvm/test/CodeGen/AArch64/
Dfloatdp_2source.ll19 %val5 = fsub float %val4, %val2
22 store volatile float %val5, float* @varfloat
47 %val5 = fsub double %val4, %val2
50 store volatile double %val5, double* @vardouble
Dextract.ll7 %val5 = or i64 %left, %right
9 ret i64 %val5
16 %val5 = or i32 %left, %right
18 ret i32 %val5
Darm64-extract.ll8 %val5 = or i64 %left, %right
10 ret i64 %val5
17 %val5 = or i32 %left, %right
19 ret i32 %val5
Daddsub-shifted.ll42 %val5 = add i64 %lhs64, %shift5
43 store volatile i64 %val5, i64* @var64
105 %val5 = add i64 %lhs64, %shift5
106 store volatile i64 %val5, i64* @var64
164 %val5 = add i64 %lhs64, %shift5
165 store volatile i64 %val5, i64* @var64
282 %val5 = sub i64 0, %shift5
283 %tst5 = icmp ne i64 %lhs64, %val5
Dregress-w29-reserved-with-fp.ll14 %val5 = load volatile i32, i32* @var
29 store volatile i32 %val5, i32* @var
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfloatdp_2source.ll19 %val5 = fsub float %val4, %val2
22 store volatile float %val5, float* @varfloat
47 %val5 = fsub double %val4, %val2
50 store volatile double %val5, double* @vardouble
Darm64-extract.ll7 %val5 = or i64 %left, %right
9 ret i64 %val5
16 %val5 = or i32 %left, %right
18 ret i32 %val5
Dextract.ll7 %val5 = or i64 %left, %right
9 ret i64 %val5
16 %val5 = or i32 %left, %right
18 ret i32 %val5
Dloop-micro-op-buffer-size-t99.ll24 ; CHECK: %val5 = add nuw nsw i32 %counter, 10
67 %val5 = add i32 %counter, 10
69 store i32 %val5, i32* %xptr5
106 %val5.2 = add i32 %counter.2, 10
108 store i32 %val5.2, i32* %xptr5.2
110 store i32 %val5.2, i32* %xptr6.2
Daddsub-shifted.ll45 %val5 = add i64 %lhs64, %shift5
46 store volatile i64 %val5, i64* @var64
108 %val5 = add i64 %lhs64, %shift5
109 store volatile i64 %val5, i64* @var64
167 %val5 = add i64 %lhs64, %shift5
168 store volatile i64 %val5, i64* @var64
285 %val5 = sub i64 0, %shift5
286 %tst5 = icmp ne i64 %lhs64, %val5
Dregress-w29-reserved-with-fp.ll14 %val5 = load volatile i32, i32* @var
29 store volatile i32 %val5, i32* @var
/external/llvm-project/clang-tools-extra/test/clang-tidy/checkers/
Dbugprone-argument-comment-literals.cpp99 double val5 = 10.0; in test() local
100 a.foo(val5); in test()
101 a.foo(-val5); in test()
Dbugprone-argument-comment-ignore-single-argument.cpp78 double val5 = 10.0; in test() local
79 a.foo(val5); in test()
/external/llvm-project/llvm/test/Transforms/LoopUnroll/X86/
Dstore_cost.ll47 %val5 = add i32 %counter, 10
49 store i32 %val5, i32* %xptr5
86 %val5.2 = add i32 %counter.2, 10
88 store i32 %val5.2, i32* %xptr5.2
90 store i32 %val5.2, i32* %xptr6.2
/external/llvm-project/llvm/test/Transforms/CodeGenPrepare/X86/
Dsink-addrmode-two-phi.ll13 %val2 = phi i64 * [ null, %entry ], [ %val5, %exit ]
24 %val5 = phi i64 * [ undef, %slowpath ], [ %val2, %start ]
/external/llvm-project/llvm/test/CodeGen/X86/
Dbb_rotate.ll31 %val5 = call i1 @foo()
32 br i1 %val5, label %.header, label %.backedge
/external/ruy/ruy/
Dpack_arm.cc2299 int8x8_t val0, val1, val2, val3, val4, val5, val6, val7, val8, val9, val10, in Pack8bitRowMajorForNeon() local
2318 val5 = load_and_convert(src_ptr + 5 * src_stride); in Pack8bitRowMajorForNeon()
2337 val5 = val0; in Pack8bitRowMajorForNeon()
2359 val5 = load_and_convert(src_ptr + 5 * src_stride); in Pack8bitRowMajorForNeon()
2385 sums16_0 = vaddq_s16(sums16_0, vaddl_s8(val4, val5)); in Pack8bitRowMajorForNeon()
2406 transpose_8bit_vals(val4, val5); in Pack8bitRowMajorForNeon()
2415 transpose_16bit_vals(val5, val7); in Pack8bitRowMajorForNeon()
2421 transpose_32bit_vals(val1, val5); in Pack8bitRowMajorForNeon()
2438 vst1q_s8(dst_ptr + 16, vcombine_s8(val5, val13)); in Pack8bitRowMajorForNeon()
/external/llvm-project/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
26 store volatile i64 %val5, i64* %addr
/external/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll13 %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
26 store volatile i64 %val5, i64* %addr

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