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/external/llvm-project/llvm/test/CodeGen/ARM/
Dfdivs.ll13 ; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
16 ; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
18 ; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
21 ; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
23 ; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
Dvdiv_combine.ll11 ; CHECK-NOT: {{vdiv|vmul}}
27 ; CHECK-NOT: {{vdiv|vmul}}
41 ; CHECK: {{vdiv|vmul}}
55 ; CHECK: {{vdiv|vmul}}
69 ; CHECK-NOT: {{vdiv|vmul}}
83 ; CHECK-NOT: {{vdiv|vmul}}
Dfparith.ll69 ;CHECK: vdiv.f32
77 ;CHECK: vdiv.f64
/external/llvm/test/CodeGen/ARM/
Dfdivs.ll13 ; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
16 ; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
18 ; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
21 ; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
23 ; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}}
Dvdiv_combine.ll11 ; CHECK-NOT: {{vdiv|vmul}}
27 ; CHECK-NOT: {{vdiv|vmul}}
41 ; CHECK: {{vdiv|vmul}}
55 ; CHECK: {{vdiv|vmul}}
69 ; CHECK-NOT: {{vdiv|vmul}}
83 ; CHECK-NOT: {{vdiv|vmul}}
Dfparith.ll69 ;CHECK: vdiv.f32
77 ;CHECK: vdiv.f64
/external/llvm-project/llvm/test/MC/RISCV/rvv/
Ddiv.s35 vdiv.vv v8, v4, v20, v0.t
36 # CHECK-INST: vdiv.vv v8, v4, v20, v0.t
41 vdiv.vv v8, v4, v20
42 # CHECK-INST: vdiv.vv v8, v4, v20
47 vdiv.vx v8, v4, a0, v0.t
48 # CHECK-INST: vdiv.vx v8, v4, a0, v0.t
53 vdiv.vx v8, v4, a0
54 # CHECK-INST: vdiv.vx v8, v4, a0
/external/llvm-project/compiler-rt/lib/builtins/arm/
Ddivsf3vfp.S21 vdiv.f32 s0, s0, s1
25 vdiv.f32 s13, s14, s15
Ddivdf3vfp.S21 vdiv.f64 d0, d0, d1
25 vdiv.f64 d5, d6, d7
/external/capstone/suite/MC/ARM/
Dsimple-fp-encoding.s.cs6 0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16
7 0x80,0x0a,0x80,0xee = vdiv.f32 s0, s1, s0
8 0xa3,0x2a,0xc2,0xee = vdiv.f32 s5, s5, s7
9 0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7
/external/llvm/test/MC/ARM/
Dsimple-fp-encoding.s13 vdiv.f64 d16, d17, d16
14 vdiv.f32 s0, s1, s0
15 vdiv.f32 s5, s7
16 vdiv.f64 d5, d7
18 @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
19 @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
20 @ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee]
21 @ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee]
Dfullfp16.s12 vdiv.f16 s0, s1, s0
13 @ ARM: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x80,0xee]
14 @ THUMB: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0xee,0x80,0x09]
Dsingle-precision-fp.s7 vdiv.f64 d4, d5, d6
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
/external/llvm-project/llvm/test/MC/ARM/
Dsimple-fp-encoding.s13 vdiv.f64 d16, d17, d16
14 vdiv.f32 s0, s1, s0
15 vdiv.f32 s5, s7
16 vdiv.f64 d5, d7
18 @ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
19 @ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
20 @ CHECK: vdiv.f32 s5, s5, s7 @ encoding: [0xa3,0x2a,0xc2,0xee]
21 @ CHECK: vdiv.f64 d5, d5, d7 @ encoding: [0x07,0x5b,0x85,0xee]
Dfullfp16.s14 vdiv.f16 s0, s1, s0
15 @ ARM: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0x09,0x80,0xee]
16 @ THUMB: vdiv.f16 s0, s1, s0 @ encoding: [0x80,0xee,0x80,0x09]
Dsingle-precision-fp.s7 vdiv.f64 d4, d5, d6
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
/external/XNNPACK/scripts/
Dgenerate-f32-vbinary.sh13 …V -D BATCH_TILE=1 -D WASM=0 -D ACTIVATION=MINMAX -o src/f32-vbinary/gen/vdiv-minmax-scalar-x1.c
14 …V -D BATCH_TILE=2 -D WASM=0 -D ACTIVATION=MINMAX -o src/f32-vbinary/gen/vdiv-minmax-scalar-x2.c
15 …V -D BATCH_TILE=4 -D WASM=0 -D ACTIVATION=MINMAX -o src/f32-vbinary/gen/vdiv-minmax-scalar-x4.c
16 …V -D BATCH_TILE=8 -D WASM=0 -D ACTIVATION=MINMAX -o src/f32-vbinary/gen/vdiv-minmax-scalar-x8.c
30 …P=DIV -D BATCH_TILE=1 -D WASM=0 -D ACTIVATION=RELU -o src/f32-vbinary/gen/vdiv-relu-scalar-x1.c
31 …P=DIV -D BATCH_TILE=2 -D WASM=0 -D ACTIVATION=RELU -o src/f32-vbinary/gen/vdiv-relu-scalar-x2.c
32 …P=DIV -D BATCH_TILE=4 -D WASM=0 -D ACTIVATION=RELU -o src/f32-vbinary/gen/vdiv-relu-scalar-x4.c
33 …P=DIV -D BATCH_TILE=8 -D WASM=0 -D ACTIVATION=RELU -o src/f32-vbinary/gen/vdiv-relu-scalar-x8.c
47 …D OP=DIV -D BATCH_TILE=1 -D WASM=0 -D ACTIVATION=LINEAR -o src/f32-vbinary/gen/vdiv-scalar-x1.c
48 …D OP=DIV -D BATCH_TILE=2 -D WASM=0 -D ACTIVATION=LINEAR -o src/f32-vbinary/gen/vdiv-scalar-x2.c
[all …]
Dgenerate-f16-vbinary.sh10 …D OP=DIV -D BATCH_TILE=8 -D ACTIVATION=MINMAX -o src/f16-vbinary/gen/vdiv-minmax-neonfp16arit…
11 …D OP=DIV -D BATCH_TILE=16 -D ACTIVATION=MINMAX -o src/f16-vbinary/gen/vdiv-minmax-neonfp16arit…
44 …est.py --tester VBinOpMicrokernelTester --spec test/f16-vdiv-minmax.yaml --output test/f16-vdiv-m…
/external/compiler-rt/lib/builtins/arm/
Ddivsf3vfp.S23 vdiv.f32 s13, s14, s15
Ddivdf3vfp.S23 vdiv.f64 d5, d6, d7
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dm7-fp.s60 vdiv.f32 s0, s2, s1
61 vdiv.f64 d0, d2, d1
189 # CHECK-NEXT: 1 16 1.00 vdiv.f32 s0, s2, s1
190 # CHECK-NEXT: 1 30 1.00 vdiv.f64 d0, d2, d1
329 … - - - - - - - - 1.00 0.50 0.50 vdiv.f32 s0, s2, s1
330 … - - - - - - - - 1.00 1.00 1.00 vdiv.f64 d0, d2, d1
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dmov-operand.ll32 ; CHECK-NEXT: vdiv.f32 s0, s0, s4
49 ; CHECK-NEXT: vdiv.f32 s0, s0, s2
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-div-expand.ll877 ; CHECK-NEXT: vdiv.f32 s11, s3, s7
878 ; CHECK-NEXT: vdiv.f32 s10, s2, s6
879 ; CHECK-NEXT: vdiv.f32 s9, s1, s5
880 ; CHECK-NEXT: vdiv.f32 s8, s0, s4
929 ; CHECK-NEXT: vdiv.f16 s8, s0, s4
933 ; CHECK-NEXT: vdiv.f16 s8, s10, s8
934 ; CHECK-NEXT: vdiv.f16 s12, s1, s5
941 ; CHECK-NEXT: vdiv.f16 s12, s14, s12
944 ; CHECK-NEXT: vdiv.f16 s12, s2, s6
949 ; CHECK-NEXT: vdiv.f16 s12, s14, s12
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dfp-encoding.txt16 # CHECK: vdiv.f64 d16, d17, d16
19 # CHECK: vdiv.f32 s0, s1, s0
/external/llvm/test/MC/Disassembler/ARM/
Dfp-encoding.txt16 # CHECK: vdiv.f64 d16, d17, d16
19 # CHECK: vdiv.f32 s0, s1, s0

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