/external/mesa3d/src/intel/compiler/ |
D | brw_vec4.h | 152 bool is_dep_ctrl_unsafe(const vec4_instruction *inst); 158 bool is_supported_64bit_region(vec4_instruction *inst, unsigned arg); 163 vec4_instruction *inst, int arg); 165 vec4_instruction *emit(vec4_instruction *inst); 167 vec4_instruction *emit(enum opcode opcode); 168 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst); 169 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, 171 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, 173 vec4_instruction *emit(enum opcode opcode, const dst_reg &dst, 177 vec4_instruction *emit_before(bblock_t *block, [all …]
|
D | brw_vec4_visitor.cpp | 31 vec4_instruction::vec4_instruction(enum opcode opcode, const dst_reg &dst, in vec4_instruction() function in brw::vec4_instruction 65 vec4_instruction * 66 vec4_visitor::emit(vec4_instruction *inst) in emit() 76 vec4_instruction * 77 vec4_visitor::emit_before(bblock_t *block, vec4_instruction *inst, in emit_before() 78 vec4_instruction *new_inst) in emit_before() 88 vec4_instruction * 92 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1, src2)); in emit() 96 vec4_instruction * 100 return emit(new(mem_ctx) vec4_instruction(opcode, dst, src0, src1)); in emit() [all …]
|
D | brw_ir_vec4.h | 269 class vec4_instruction : public backend_instruction { 271 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction) 273 vec4_instruction(enum opcode opcode, 370 inline vec4_instruction * 372 vec4_instruction *inst) in set_predicate_inv() 382 inline vec4_instruction * 383 set_predicate(enum brw_predicate pred, vec4_instruction *inst) in set_predicate() 392 inline vec4_instruction * 393 set_condmod(enum brw_conditional_mod mod, vec4_instruction *inst) in set_condmod() 403 inline vec4_instruction * [all …]
|
D | brw_vec4_cse.cpp | 41 vec4_instruction *generator; 49 is_expression(const vec4_instruction *const inst) in is_expression() 98 operands_match(const vec4_instruction *a, const vec4_instruction *b) in operands_match() 143 instructions_match(vec4_instruction *a, vec4_instruction *b) in instructions_match() 174 foreach_inst_in_block (vec4_instruction, inst, block) { in opt_cse_local() 218 vec4_instruction *copy = in opt_cse_local() 239 vec4_instruction *copy = in opt_cse_local() 253 vec4_instruction *prev = (vec4_instruction *)inst->prev; in opt_cse_local()
|
D | brw_vec4.cpp | 150 vec4_instruction::is_send_from_grf() const in is_send_from_grf() 188 vec4_instruction::has_source_and_destination_hazard() const in has_source_and_destination_hazard() 207 vec4_instruction::size_read(unsigned arg) const in size_read() 239 vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo) in can_do_source_mods() 254 vec4_instruction::can_do_cmod() in can_do_cmod() 274 vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo) in can_do_writemask() 310 vec4_instruction::can_change_types() const in can_change_types() 329 vec4_instruction::implied_mrf_writes() const in implied_mrf_writes() 409 vec4_instruction *imm_inst[4]; in opt_vector_float() 413 foreach_inst_in_block_safe(vec4_instruction, inst, block) { in opt_vector_float() [all …]
|
D | brw_vec4_vs_visitor.cpp | 46 vec4_instruction * 55 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE); in emit_urb_write_opcode() 78 vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0); in emit_urb_slot()
|
D | test_vec4_dead_code_eliminate.cpp | 80 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode() 138 vec4_instruction *test_cmp = in TEST_F() 144 vec4_instruction *test_mov = in TEST_F() 150 vec4_instruction *test_sel = in TEST_F()
|
D | brw_vec4_reg_allocate.cpp | 55 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate_trivial() 75 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate_trivial() 226 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate() 268 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in reg_allocate() 302 can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, in can_use_scratch_for_source() 315 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev; in can_use_scratch_for_source() 317 prev_inst = (vec4_instruction *) prev_inst->prev) { in can_use_scratch_for_source() 398 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in evaluate_spill_costs() 512 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in spill_reg()
|
D | test_vec4_register_coalesce.cpp | 85 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode() 137 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F() 161 vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f))); in TEST_F() 184 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F() 202 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F() 228 vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2)); in TEST_F()
|
D | brw_vec4_tes.cpp | 61 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_payload() 103 vec4_instruction * 112 vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE); in emit_urb_write_opcode() 198 vec4_instruction *read = in nir_emit_intrinsic()
|
D | brw_vec4_cmod_propagation.cpp | 39 writemasks_incompatible(const vec4_instruction *earlier, in writemasks_incompatible() 40 const vec4_instruction *later) in writemasks_incompatible() 55 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) { in opt_cmod_propagation_local() 85 foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, inst) { in opt_cmod_propagation_local() 191 vec4_instruction *mov = v->MOV(scan_inst->dst, temp); in opt_cmod_propagation_local()
|
D | test_vec4_copy_propagation.cpp | 82 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode() 137 vec4_instruction *test_mov = in TEST_F() 166 vec4_instruction *test_mov = in TEST_F()
|
D | brw_vec4_copy_propagation.cpp | 44 is_direct_copy(vec4_instruction *inst) in is_direct_copy() 58 is_dominated_by_previous_instruction(vec4_instruction *inst) in is_dominated_by_previous_instruction() 67 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch) in is_channel_updated() 126 try_constant_propagate(vec4_instruction *inst, in try_constant_propagate() 303 vec4_instruction *inst, int arg, in try_copy_propagate() 463 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in opt_copy_propagation()
|
D | brw_vec4_gs_visitor.cpp | 100 foreach_block_and_inst(block, vec4_instruction, inst, cfg) { in setup_varying_inputs() 168 vec4_instruction *inst = emit(GS_OPCODE_SET_DWORD_2, r0, brw_imm_ud(0u)); in emit_prolog() 220 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_thread_end() 245 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_urb_write_header() 252 vec4_instruction * 261 vec4_instruction *inst = emit(GS_OPCODE_URB_WRITE); in emit_urb_write_opcode() 336 vec4_instruction *inst = emit(MOV(mrf_reg, r0)); in emit_control_data_bits() 465 vec4_instruction *inst = in gs_emit_vertex()
|
D | gen6_gs_visitor.cpp | 74 vec4_instruction *inst = emit(MOV(dst_reg(MRF, 1), in emit_prolog() 169 vec4_instruction *inst = emit(MOV(dst, src_reg(tmp))); in gs_emit_vertex() 225 vec4_instruction *inst = emit(CMP(dst_null_ud(), in gs_end_primitive() 293 vec4_instruction *inst = NULL; in emit_urb_write_opcode() 355 vec4_instruction *inst = NULL; in emit_thread_end() 612 vec4_instruction *inst = emit(MOV(dst_reg(destination_indices), in xfb_write() 666 vec4_instruction *inst = emit(GS_OPCODE_SVB_SET_DST_INDEX, in xfb_program()
|
D | brw_vec4_generator.cpp | 33 vec4_instruction *inst, in generate_math1_gen4() 56 vec4_instruction *inst, in generate_math_gen6() 75 vec4_instruction *inst, in generate_math2_gen4() 111 vec4_instruction *inst, in generate_tex() 345 generate_vs_urb_write(struct brw_codegen *p, vec4_instruction *inst) in generate_vs_urb_write() 359 generate_gs_urb_write(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_urb_write() 374 generate_gs_urb_write_allocate(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_urb_write_allocate() 399 generate_gs_thread_end(struct brw_codegen *p, vec4_instruction *inst) in generate_gs_thread_end() 488 vec4_instruction *inst, in generate_gs_svb_write() 530 vec4_instruction *inst, in generate_gs_svb_set_destination_index() [all …]
|
D | brw_vec4_tcs.cpp | 100 vec4_instruction *inst; in emit_thread_end() 162 vec4_instruction *inst; in emit_input_urb_read() 197 vec4_instruction *inst; in emit_output_urb_read() 205 vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header)); in emit_output_urb_read() 228 vec4_instruction *inst; in emit_urb_write()
|
D | brw_vec4_tes.h | 57 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
|
D | brw_vec4_vs.h | 48 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
|
D | test_vec4_cmod_propagation.cpp | 90 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) in emit_urb_write_opcode() 113 static vec4_instruction * 116 vec4_instruction *inst = (vec4_instruction *)block->start(); in instruction() 118 inst = (vec4_instruction *)inst->next; in instruction() 834 vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE); in TEST_F() 869 vec4_instruction *inst = bld.CMP(dest_null, src0, src1, BRW_CONDITIONAL_GE); in TEST_F()
|
D | brw_vec4_gs_visitor.h | 59 virtual vec4_instruction *emit_urb_write_opcode(bool complete);
|
D | brw_vec4_tcs.h | 75 virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */) { return NULL; } in emit_urb_write_opcode()
|
D | brw_vec4_live_variables.cpp | 75 foreach_inst_in_block(vec4_instruction, inst, block) { in setup_def_use() 275 foreach_block_and_inst(block, vec4_instruction, inst, s->cfg) { in validate()
|
D | brw_vec4_nir.cpp | 102 vec4_instruction *inst = emit(MOV(dst_null_d(), condition)); in nir_emit_if() 445 vec4_instruction *inst = new(mem_ctx) in nir_emit_intrinsic() 446 vec4_instruction(SHADER_OPCODE_GET_BUFFER_SIZE, result_dst); in nir_emit_intrinsic() 707 vec4_instruction *fence = in nir_emit_intrinsic() 822 vec4_instruction *inst; in emit_find_msb_using_lzd() 1103 vec4_instruction *inst; in nir_emit_alu() 1548 vec4_instruction *inst = emit(MOV(dst_null_df(), value)); in nir_emit_alu() 2149 vec4_instruction * 2151 bblock_t *block, vec4_instruction *ref) in shuffle_64bit_data()
|
D | brw_vec4_dead_code_eliminate.cpp | 55 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) { in dead_code_eliminate()
|