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Searched refs:xop (Results 1 – 25 of 143) sorted by relevance

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/external/llvm/test/Transforms/InstCombine/
Dx86-xop.ll7 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP1]])
13 %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
24 %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
32 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP1]])
40 %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
53 %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
64 %1 = tail call <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64> %a, <2 x i64> %b)
74 %1 = tail call <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64> %a, <2 x i64> %b)
84 %1 = tail call <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64> %a, <2 x i64> %b)
94 %1 = tail call <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64> %a, <2 x i64> %b)
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/X86/
Dx86-xop.ll6 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[A:%.*]…
10 %2 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %1)
17 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP1]])
23 %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
34 %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
41 ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[A:%.*]])
47 %4 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %3)
54 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP1]])
62 %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
75 %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
[all …]
/external/llvm/test/CodeGen/X86/
Dxop-intrinsics-x86_64-upgrade.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double>…
18 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %vec, <2 x double…
27 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double>…
30 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x double>, i8) nounwin…
37 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x dou…
46 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %vec, <4 x do…
55 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x dou…
58 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nou…
65 …%res = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2…
[all …]
Dxop-intrinsics-x86_64.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a…
18 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %vec, <2 x i64> %…
27 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %v…
30 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x i64>, i8) nounwind r…
37 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64…
46 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %vec, <4 x i6…
55 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64…
58 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x i64>, i8) nounwi…
65 …%res = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x i32> %a2, …
[all …]
Dcommute-xop.ll1 ; RUN: llc -O3 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx,+xop < %s | FileCheck %s
7 %2 = call <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8> %1, <16 x i8> %a1, i8 0) ; vpcomltb
10 declare <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8>, <16 x i8>, i8) nounwind readnone
16 %2 = call <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32> %1, <4 x i32> %a1, i8 1) ; vpcomled
19 declare <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32>, <4 x i32>, i8) nounwind readnone
25 %2 = call <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64> %1, <2 x i64> %a1, i8 2) ; vpcomgtq
28 declare <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64>, <2 x i64>, i8) nounwind readnone
34 %2 = call <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8> %1, <16 x i8> %a1, i8 3) ; vpcomgeub
37 declare <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8>, <16 x i8>, i8) nounwind readnone
43 %2 = call <4 x i32> @llvm.x86.xop.vpcomud(<4 x i32> %1, <4 x i32> %a1, i8 4) ; vpcomequd
[all …]
Dstack-folding-xop.ll1 ; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop < %s | FileCheck …
15 %2 = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %a0)
18 declare <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double>) nounwind readnone
24 %2 = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %a0)
27 declare <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double>) nounwind readnone
33 %2 = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %a0)
36 declare <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float>) nounwind readnone
42 %2 = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %a0)
45 declare <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float>) nounwind readnone
51 %2 = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %a0)
[all …]
Dxop-intrinsics-fast-isel.ll2 ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s --ch…
3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s --…
5 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/xop-builtins.c
20 %res = call <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16> %arg0, <8 x i16> %arg1, <8 x i16> %arg2)
24 declare <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
39 %res = call <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16> %arg0, <8 x i16> %arg1, <8 x i16> %arg2)
43 declare <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
58 %res = call <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16> %arg0, <8 x i16> %arg1, <4 x i32> %arg2)
62 declare <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
77 %res = call <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16> %arg0, <8 x i16> %arg1, <4 x i32> %arg2)
[all …]
Dvector-shuffle-combining-xop.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+xop | FileCheck %s
5 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x i64>, i8) nounwind r…
6 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x i64>, i8) nounwi…
8 declare <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float>, <4 x float>, <4 x i32>, i8) nounwind read…
9 declare <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float>, <8 x float>, <8 x i32>, i8) nounwind …
11 declare <16 x i8> @llvm.x86.xop.vpperm(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
18 …%res0 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a1, <2 x double> %a0, <2 x i64> <…
19 …%res1 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %res0, <2 x double> undef, <2 x i6…
28 …%res0 = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a1, <4 x double> %a0, <4 x i6…
[all …]
Dxop-mask-comments.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefix=X32
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefix=X64
19 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 1…
33 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> undef, <16 x i8> <i8 31, i8…
47 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 1…
61 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> <i8 31, i8 1…
75 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> <i8 31, i8 1…
90 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 1…
108 …%1 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> <i64…
122 …%1 = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64> …
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dxop-intrinsics-x86_64-upgrade.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double>…
18 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %vec, <2 x double…
27 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x double>…
30 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x double>, i8) nounwin…
37 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x dou…
46 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %vec, <4 x do…
55 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x dou…
58 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x double>, i8) nou…
65 …%res = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2…
[all …]
Dxop-intrinsics-x86_64.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
9 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %a…
18 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %vec, <2 x i64> %…
27 …%res = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> %v…
30 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x i64>, i8) nounwind r…
37 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64…
46 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %vec, <4 x i6…
55 …%res = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64…
58 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x i64>, i8) nounwi…
65 …%res = call <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float> %a0, <4 x float> %a1, <4 x i32> %a2, …
[all …]
Dxop-intrinsics-fast-isel.ll2 ; RUN: llc < %s -fast-isel -mtriple=i686-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
3 ; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx,+fma4,+xop | FileCheck %s
5 ; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/xop-builtins.c
15 %res = call <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16> %arg0, <8 x i16> %arg1, <8 x i16> %arg2)
19 declare <8 x i16> @llvm.x86.xop.vpmacssww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
29 %res = call <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16> %arg0, <8 x i16> %arg1, <8 x i16> %arg2)
33 declare <8 x i16> @llvm.x86.xop.vpmacsww(<8 x i16>, <8 x i16>, <8 x i16>) nounwind readnone
43 %res = call <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16> %arg0, <8 x i16> %arg1, <4 x i32> %arg2)
47 declare <4 x i32> @llvm.x86.xop.vpmacsswd(<8 x i16>, <8 x i16>, <4 x i32>) nounwind readnone
57 %res = call <4 x i32> @llvm.x86.xop.vpmacswd(<8 x i16> %arg0, <8 x i16> %arg1, <4 x i32> %arg2)
[all …]
Dcommute-xop.ll2 ; RUN: llc < %s -disable-peephole -mtriple=i686-unknown-unknown -mattr=+avx,+xop | FileCheck %s --c…
3 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s -…
17 %2 = call <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8> %1, <16 x i8> %a1, i8 0) ; vpcomltb
20 declare <16 x i8> @llvm.x86.xop.vpcomb(<16 x i8>, <16 x i8>, i8) nounwind readnone
34 %2 = call <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32> %1, <4 x i32> %a1, i8 1) ; vpcomled
37 declare <4 x i32> @llvm.x86.xop.vpcomd(<4 x i32>, <4 x i32>, i8) nounwind readnone
51 %2 = call <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64> %1, <2 x i64> %a1, i8 2) ; vpcomgtq
54 declare <2 x i64> @llvm.x86.xop.vpcomq(<2 x i64>, <2 x i64>, i8) nounwind readnone
68 %2 = call <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8> %1, <16 x i8> %a1, i8 3) ; vpcomgeub
71 declare <16 x i8> @llvm.x86.xop.vpcomub(<16 x i8>, <16 x i8>, i8) nounwind readnone
[all …]
Dstack-folding-xop.ll2 ; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop < %s | FileCheck …
22 %2 = call <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double> %a0)
25 declare <2 x double> @llvm.x86.xop.vfrcz.pd(<2 x double>) nounwind readnone
37 %2 = call <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double> %a0)
40 declare <4 x double> @llvm.x86.xop.vfrcz.pd.256(<4 x double>) nounwind readnone
52 %2 = call <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float> %a0)
55 declare <4 x float> @llvm.x86.xop.vfrcz.ps(<4 x float>) nounwind readnone
67 %2 = call <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float> %a0)
70 declare <8 x float> @llvm.x86.xop.vfrcz.ps.256(<8 x float>) nounwind readnone
82 %2 = call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %a0)
[all …]
Dxop-mask-comments.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefixes=CHEC…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefixes=CH…
14 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 1…
23 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> undef, <16 x i8> <i8 31, i8…
32 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 1…
41 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> <i8 31, i8 1…
50 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> <i8 31, i8 1…
65 …%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 1…
81 …%1 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a0, <2 x double> %a1, <2 x i64> <i64…
90 …%1 = call <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double> %a0, <4 x double> %a1, <4 x i64> …
[all …]
Dvector-shuffle-combining-xop.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefixes=CHEC…
3 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2,+xop | FileCheck %s --check-prefixes=CHE…
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+xop | FileCheck %s --check-prefixes=CH…
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+xop | FileCheck %s --check-prefixes=C…
7 declare <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double>, <2 x double>, <2 x i64>, i8) nounwind r…
8 declare <4 x double> @llvm.x86.xop.vpermil2pd.256(<4 x double>, <4 x double>, <4 x i64>, i8) nounwi…
10 declare <4 x float> @llvm.x86.xop.vpermil2ps(<4 x float>, <4 x float>, <4 x i32>, i8) nounwind read…
11 declare <8 x float> @llvm.x86.xop.vpermil2ps.256(<8 x float>, <8 x float>, <8 x i32>, i8) nounwind …
13 declare <16 x i8> @llvm.x86.xop.vpperm(<16 x i8>, <16 x i8>, <16 x i8>) nounwind readnone
20 …%res0 = call <2 x double> @llvm.x86.xop.vpermil2pd(<2 x double> %a1, <2 x double> %a0, <2 x i64> <…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h68 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) argument
69 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) argument
70 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) argument
71 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) argument
72 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) argument
74 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) argument
75 #define ppFromXOP3of3(xop) ((xop) & 0x3) argument
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h66 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) argument
67 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) argument
68 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) argument
69 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) argument
70 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) argument
72 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) argument
73 #define ppFromXOP3of3(xop) ((xop) & 0x3) argument
/external/llvm-project/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h65 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) argument
66 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) argument
67 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) argument
68 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) argument
69 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) argument
71 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) argument
72 #define ppFromXOP3of3(xop) ((xop) & 0x3) argument
/external/capstone/arch/X86/
DX86DisassemblerDecoder.h73 #define rFromXOP2of3(xop) (((~(xop)) & 0x80) >> 7) argument
74 #define xFromXOP2of3(xop) (((~(xop)) & 0x40) >> 6) argument
75 #define bFromXOP2of3(xop) (((~(xop)) & 0x20) >> 5) argument
76 #define mmmmmFromXOP2of3(xop) ((xop) & 0x1f) argument
77 #define wFromXOP3of3(xop) (((xop) & 0x80) >> 7) argument
79 #define lFromXOP3of3(xop) (((xop) & 0x4) >> 2) argument
80 #define ppFromXOP3of3(xop) ((xop) & 0x3) argument
/external/clang/include/clang/Basic/
DBuiltinsX86.def816 TARGET_BUILTIN(__builtin_ia32_vpmacssww, "V8sV8sV8sV8s", "", "xop")
817 TARGET_BUILTIN(__builtin_ia32_vpmacsww, "V8sV8sV8sV8s", "", "xop")
818 TARGET_BUILTIN(__builtin_ia32_vpmacsswd, "V4iV8sV8sV4i", "", "xop")
819 TARGET_BUILTIN(__builtin_ia32_vpmacswd, "V4iV8sV8sV4i", "", "xop")
820 TARGET_BUILTIN(__builtin_ia32_vpmacssdd, "V4iV4iV4iV4i", "", "xop")
821 TARGET_BUILTIN(__builtin_ia32_vpmacsdd, "V4iV4iV4iV4i", "", "xop")
822 TARGET_BUILTIN(__builtin_ia32_vpmacssdql, "V2LLiV4iV4iV2LLi", "", "xop")
823 TARGET_BUILTIN(__builtin_ia32_vpmacsdql, "V2LLiV4iV4iV2LLi", "", "xop")
824 TARGET_BUILTIN(__builtin_ia32_vpmacssdqh, "V2LLiV4iV4iV2LLi", "", "xop")
825 TARGET_BUILTIN(__builtin_ia32_vpmacsdqh, "V2LLiV4iV4iV2LLi", "", "xop")
[all …]
/external/llvm-project/clang/include/clang/Basic/
DBuiltinsX86.def798 TARGET_BUILTIN(__builtin_ia32_vpmacssww, "V8sV8sV8sV8s", "ncV:128:", "xop")
799 TARGET_BUILTIN(__builtin_ia32_vpmacsww, "V8sV8sV8sV8s", "ncV:128:", "xop")
800 TARGET_BUILTIN(__builtin_ia32_vpmacsswd, "V4iV8sV8sV4i", "ncV:128:", "xop")
801 TARGET_BUILTIN(__builtin_ia32_vpmacswd, "V4iV8sV8sV4i", "ncV:128:", "xop")
802 TARGET_BUILTIN(__builtin_ia32_vpmacssdd, "V4iV4iV4iV4i", "ncV:128:", "xop")
803 TARGET_BUILTIN(__builtin_ia32_vpmacsdd, "V4iV4iV4iV4i", "ncV:128:", "xop")
804 TARGET_BUILTIN(__builtin_ia32_vpmacssdql, "V2OiV4iV4iV2Oi", "ncV:128:", "xop")
805 TARGET_BUILTIN(__builtin_ia32_vpmacsdql, "V2OiV4iV4iV2Oi", "ncV:128:", "xop")
806 TARGET_BUILTIN(__builtin_ia32_vpmacssdqh, "V2OiV4iV4iV2Oi", "ncV:128:", "xop")
807 TARGET_BUILTIN(__builtin_ia32_vpmacsdqh, "V2OiV4iV4iV2Oi", "ncV:128:", "xop")
[all …]
/external/XNNPACK/scripts/
Dgenerate-qs8-vadd.sh45 …8-vadd/sse-mul32-ld32.c.in -D BATCH_TILE=8 -D SSE=5 -o src/qs8-vadd/gen/minmax-xop-mul32-ld32-x8.c
46 …-vadd/sse-mul32-ld32.c.in -D BATCH_TILE=16 -D SSE=5 -o src/qs8-vadd/gen/minmax-xop-mul32-ld32-x16.c
47 …-vadd/sse-mul32-ld32.c.in -D BATCH_TILE=24 -D SSE=5 -o src/qs8-vadd/gen/minmax-xop-mul32-ld32-x24.c
48 …-vadd/sse-mul32-ld32.c.in -D BATCH_TILE=32 -D SSE=5 -o src/qs8-vadd/gen/minmax-xop-mul32-ld32-x32.c
65 …vaddc/sse-mul32-ld32.c.in -D BATCH_TILE=8 -D SSE=5 -o src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x8.c
66 …addc/sse-mul32-ld32.c.in -D BATCH_TILE=16 -D SSE=5 -o src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x16.c
67 …addc/sse-mul32-ld32.c.in -D BATCH_TILE=24 -D SSE=5 -o src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x24.c
68 …addc/sse-mul32-ld32.c.in -D BATCH_TILE=32 -D SSE=5 -o src/qs8-vaddc/gen/minmax-xop-mul32-ld32-x32.c
Dgenerate-qs8-gemm.sh111 …mm/MRx4c2-sse.c.in -D MR=1 -D SSE=5 -D VARIANT=LD64 -o src/qs8-gemm/gen/1x4c2-minmax-xop-ld64.c
112 …mm/MRx4c2-sse.c.in -D MR=4 -D SSE=5 -D VARIANT=LD64 -o src/qs8-gemm/gen/4x4c2-minmax-xop-ld64.c
123 …m/MRx4c2-sse.c.in -D MR=1 -D SSE=5 -D VARIANT=LD128 -o src/qs8-gemm/gen/1x4c2-minmax-xop-ld128.c
124 …m/MRx4c2-sse.c.in -D MR=4 -D SSE=5 -D VARIANT=LD128 -o src/qs8-gemm/gen/4x4c2-minmax-xop-ld128.c
135 …gemm/MRx4c2-sse.c.in -D MR=1 -D SSE=5 -D VARIANT=EXTENDED -o src/qs8-gemm/gen/1x4c2-xw-minmax-xop.c
136 …gemm/MRx4c2-sse.c.in -D MR=4 -D SSE=5 -D VARIANT=EXTENDED -o src/qs8-gemm/gen/4x4c2-xw-minmax-xop.c
151 …mm/MRx4c8-sse.c.in -D MR=1 -D SSE=5 -D VARIANT=LD64 -o src/qs8-gemm/gen/1x4c8-minmax-xop-ld64.c
152 …mm/MRx4c8-sse.c.in -D MR=2 -D SSE=5 -D VARIANT=LD64 -o src/qs8-gemm/gen/2x4c8-minmax-xop-ld64.c
153 …mm/MRx4c8-sse.c.in -D MR=3 -D SSE=5 -D VARIANT=LD64 -o src/qs8-gemm/gen/3x4c8-minmax-xop-ld64.c
167 …m/MRx4c8-sse.c.in -D MR=1 -D SSE=5 -D VARIANT=LD128 -o src/qs8-gemm/gen/1x4c8-minmax-xop-ld128.c
[all …]
/external/llvm-project/polly/test/ScopInfo/
Ddo-not-model-error-block-accesses.ll27 …512er,-avx512f,-avx512pf,-avx512vl,-fma4,-prfchw,-rdseed,-sha,-sse4a,-tbm,-xop,-xsavec,-xsaves" "u…
28 …512er,-avx512f,-avx512pf,-avx512vl,-fma4,-prfchw,-rdseed,-sha,-sse4a,-tbm,-xop,-xsavec,-xsaves" "u…

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