| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-fceil.mir | 17 ; SI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
18 ; SI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
25 ; CI: [[FCEIL:%[0-9]+]]:_(s32) = G_FCEIL [[FPEXT]]
26 ; CI: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FCEIL]](s32)
32 ; VI: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
33 ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
38 ; GFX9: [[FCEIL:%[0-9]+]]:_(s16) = G_FCEIL [[TRUNC]]
39 ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCEIL]](s16)
106 ; SI: [[FCEIL:%[0-9]+]]:_(s64) = G_FCEIL [[COPY]]
107 ; SI: $vgpr0_vgpr1 = COPY [[FCEIL]](s64)
[all …]
|
| D | regbankselect-fceil.mir | 15 ; CHECK: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
29 ; CHECK: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
|
| D | inst-select-fceil.s16.mir | 18 ; GCN: [[FCEIL:%[0-9]+]]:sreg_32(s16) = G_FCEIL [[TRUNC]]
19 ; GCN: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FCEIL]](s16)
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
|
| D | BasicTTIImpl.h | 785 ISDs.push_back(ISD::FCEIL); in getIntrinsicInstrCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 58 FUNCTION(ceil, 1, 0, experimental_constrained_ceil, FCEIL)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 642 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 72 DAG_FUNCTION(ceil, 1, 0, experimental_constrained_ceil, FCEIL)
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 806 FCEIL, enumerator
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 303 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
356 Opcode = ISD::FCEIL; break; in mightUseCTR()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 313 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
372 Opcode = ISD::FCEIL; break; in mightUseCTR()
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 472 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
579 Opcode = ISD::FCEIL; break; in mightUseCTR()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 164 case ISD::FCEIL: return "fceil"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 80 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
1020 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
1870 case ISD::FCEIL: in PromoteFloatResult()
|
| D | LegalizeVectorOps.cpp | 318 case ISD::FCEIL: in LegalizeOp()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
|
| /external/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1149 VIR_A_ALU1(FCEIL) in VIR_A_ALU2()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 205 case ISD::FCEIL: return "fceil"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 76 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
1138 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
2108 case ISD::FCEIL: in PromoteFloatResult()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 207 case ISD::FCEIL: return "fceil"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 76 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
1176 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
2214 case ISD::FCEIL: in PromoteFloatResult()
2578 case ISD::FCEIL: in SoftPromoteHalfResult()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 99 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
192 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 238 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
277 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in AMDGPUTargetLowering()
411 setOperationAction(ISD::FCEIL, VT, Expand); in AMDGPUTargetLowering()
713 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 99 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
182 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-fp-rounding.ll | 4 ; FCEIL
|