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Searched refs:Reg0 (Results 1 – 25 of 66) sorted by relevance

123

/external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/
DTargetTest.cpp87 const unsigned Reg0 = Mips::T0; in TEST_F() local
88 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)), in TEST_F()
89 ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true))); in TEST_F()
99 const unsigned Reg0 = Mips::T0_64; in TEST_F() local
100 EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)), in TEST_F()
101 ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false))); in TEST_F()
/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DLocked.cpp86 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
89 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
93 __ mov(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
97 __ xchg(IceType_i##Size, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
99 __ And(IceType_i32, GPRRegister::Encoded_Reg_##Reg0, \ in TEST_F()
108 ASSERT_EQ(V1, test.Reg0()) << TestString; \ in TEST_F()
112 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
114 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
117 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
119 if (GPRRegister::Encoded_Reg_##Reg0 < 4 && \ in TEST_F()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsTargetStreamer.h119 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
123 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
125 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
127 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
129 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
131 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
133 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
137 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
/external/llvm-project/llvm/lib/Target/Mips/
DMipsTargetStreamer.h120 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
124 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
126 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
128 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
130 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
132 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
134 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
136 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
138 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DLocked.cpp89 #define TestImplRegReg(Reg0, Value0, Reg1, Value1, Size) \ in TEST_F() argument
92 "(" #Reg0 "," #Value0 ", " #Reg1 ", " #Value1 ", " #Size ")"; \ in TEST_F()
96 __ mov(IceType_i##Size, Encoded_GPR_##Reg0(), Immediate(Value0)); \ in TEST_F()
98 __ xchg(IceType_i##Size, Encoded_GPR_##Reg0(), Encoded_GPR_##Reg1()); \ in TEST_F()
99 __ And(IceType_i32, Encoded_GPR_##Reg0(), Immediate(Mask##Size)); \ in TEST_F()
106 ASSERT_EQ(V1, test.Reg0()) << TestString; \ in TEST_F()
110 #define TestImplSize(Reg0, Reg1, Size) \ in TEST_F() argument
112 TestImplRegReg(Reg0, 0xa2b34567, Reg1, 0x0507ddee, Size); \ in TEST_F()
115 #define TestImpl(Reg0, Reg1) \ in TEST_F() argument
117 TestImplSize(Reg0, Reg1, 8); \ in TEST_F()
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/external/llvm/lib/Target/Mips/
DMipsTargetStreamer.h103 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
107 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
109 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
111 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
113 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
115 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
117 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
/external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp169 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
178 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
182 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
188 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
190 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
193 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
195 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
208 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
213 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp166 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
170 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
175 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
185 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
187 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
190 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
192 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
205 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
210 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
[all …]
/external/llvm/include/llvm/MC/
DMCRegisterInfo.h613 uint16_t Reg0; variable
616 MCRegUnitRootIterator() : Reg0(0), Reg1(0) {} in MCRegUnitRootIterator()
619 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
625 return Reg0;
630 return Reg0; in isValid()
636 Reg0 = Reg1;
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp129 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
133 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
138 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
142 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
148 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
150 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
153 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
155 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
168 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp237 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
238 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
242 if (Reg0.isVirtual()) { in runOnMachineFunction()
244 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp240 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
241 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
245 if (Register::isVirtualRegister(Reg0)) { in runOnMachineFunction()
247 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp243 unsigned Reg0 = Op0.getReg(); in runOnMachineFunction() local
244 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
248 if (TargetRegisterInfo::isVirtualRegister(Reg0)) { in runOnMachineFunction()
250 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1861 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
1881 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc); in SelectVLD()
1884 Ops.push_back(Reg0); in SelectVLD()
1897 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
1910 Ops.push_back(Reg0); in SelectVLD()
1914 Ops.push_back(Reg0); in SelectVLD()
1991 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2036 Ops.push_back(Reg0); in SelectVST()
2040 Ops.push_back(Reg0); in SelectVST()
2065 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
DThumb2SizeReduction.cpp706 unsigned Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
712 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
715 if (Reg0 != Reg2) { in ReduceTo2Addr()
718 if (Reg1 != Reg0) in ReduceTo2Addr()
725 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
730 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
737 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp2063 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2085 Ops.push_back(Reg0); in SelectVLD()
2088 Ops.push_back(Reg0); in SelectVLD()
2101 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
2114 Ops.push_back(Reg0); in SelectVLD()
2118 Ops.push_back(Reg0); in SelectVLD()
2195 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2242 Ops.push_back(Reg0); in SelectVST()
2246 Ops.push_back(Reg0); in SelectVST()
2271 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
DThumb2SizeReduction.cpp746 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
752 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
755 if (Reg0 != Reg2) { in ReduceTo2Addr()
758 if (Reg1 != Reg0) in ReduceTo2Addr()
765 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
770 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
777 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp2113 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2135 Ops.push_back(Reg0); in SelectVLD()
2138 Ops.push_back(Reg0); in SelectVLD()
2151 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
2164 Ops.push_back(Reg0); in SelectVLD()
2168 Ops.push_back(Reg0); in SelectVLD()
2248 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2295 Ops.push_back(Reg0); in SelectVST()
2299 Ops.push_back(Reg0); in SelectVST()
2324 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
DThumb2SizeReduction.cpp756 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
762 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
765 if (Reg0 != Reg2) { in ReduceTo2Addr()
768 if (Reg1 != Reg0) in ReduceTo2Addr()
775 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
780 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
787 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/
DMCRegisterInfo.h739 uint16_t Reg0 = 0; variable
747 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
753 return Reg0;
758 return Reg0; in isValid()
764 Reg0 = Reg1;
/external/llvm-project/llvm/include/llvm/MC/
DMCRegisterInfo.h740 uint16_t Reg0 = 0; variable
748 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
754 return Reg0;
759 return Reg0; in isValid()
765 Reg0 = Reg1;
/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp165 Register Reg0; in TEST_F() local
168 m_GICmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1))); in TEST_F()
171 EXPECT_EQ(Copies[0], Reg0); in TEST_F()
190 Register Reg0; in TEST_F() local
193 m_GFCmp(m_Pred(Pred), m_Reg(Reg0), m_Reg(Reg1))); in TEST_F()
196 EXPECT_EQ(Copies[0], Reg0); in TEST_F()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
247 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
247 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/external/llvm-project/llvm/lib/Target/X86/
DX86ExpandPseudo.cpp378 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
382 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandMI()
412 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in ExpandMI() local
425 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in ExpandMI()

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