Home
last modified time | relevance | path

Searched refs:Rt2 (Results 1 – 25 of 57) sorted by relevance

123

/external/llvm/test/MC/AArch64/
Darm64-diags.s155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-diags.s155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
[all …]
/external/capstone/arch/AArch64/
DAArch64Disassembler.c1187 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeExclusiveLdStInstruction() local
1233 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1242 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1251 Rt == Rt2) in DecodeExclusiveLdStInstruction()
1263 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodePairLdStInstruction() local
1321 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1334 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1345 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1356 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1367 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-unpredictable.txt46 # Unpredictable if Rt == Rt2 on a load.
67 # Unpredictable if Rt == Rt2 on a load.
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-unpredictable.txt46 # Unpredictable if Rt == Rt2 on a load.
67 # Unpredictable if Rt == Rt2 on a load.
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7-xfail.txt9 # Rt == Rt2 is UNPREDICTABLE
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7-xfail.txt9 # Rt == Rt2 is UNPREDICTABLE
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1086 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeExclusiveLdStInstruction() local
1140 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1149 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1158 Rt == Rt2) in DecodeExclusiveLdStInstruction()
1169 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodePairLdStInstruction() local
1228 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1241 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1252 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1263 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1274 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1292 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeExclusiveLdStInstruction() local
1346 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1355 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1364 Rt == Rt2) in DecodeExclusiveLdStInstruction()
1375 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodePairLdStInstruction() local
1439 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1452 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1463 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1474 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1485 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
[all …]
/external/capstone/arch/ARM/
DARMDisassembler.c1684 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction() local
1708 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1712 if (Rt2 == 15) in DecodeAddrMode3Instruction()
1731 if (Rt2 == 15) in DecodeAddrMode3Instruction()
1737 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
1741 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
4884 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); in DecodeVMOVSRR() local
4889 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
4898 if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) in DecodeVMOVSRR()
4911 unsigned Rt2 = fieldFromInstruction_4(Insn, 16, 4); in DecodeVMOVRRS() local
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1295 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeExclusiveLdStInstruction() local
1349 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1358 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1367 Rt == Rt2) in DecodeExclusiveLdStInstruction()
1378 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodePairLdStInstruction() local
1442 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1455 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1466 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1477 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1488 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1633 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction() local
1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1661 if (Rt2 == 15) in DecodeAddrMode3Instruction()
1680 if (Rt2 == 15) in DecodeAddrMode3Instruction()
1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
1690 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
4931 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVSRR() local
4936 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
4945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) in DecodeVMOVSRR()
4957 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVRRS() local
[all …]
/external/llvm-project/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp2006 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction() local
2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2034 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2053 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2059 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
2063 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
5471 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVSRR() local
5476 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
5485 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) in DecodeVMOVSRR()
5497 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVRRS() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1985 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction() local
2009 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2013 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2032 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2038 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
2042 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
5448 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVSRR() local
5453 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
5462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) in DecodeVMOVSRR()
5474 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVRRS() local
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td1033 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1034 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1039 bits<4> Rt2;
1045 let Inst{19-16} = Rt2;
1055 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1060 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1061 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
1065 bits<4> Rt2;
1071 let Inst{19-16} = Rt2;
1086 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
[all …]
DARMInstrThumb2.td1279 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1281 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1449 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1450 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1557 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1559 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1564 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1566 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1571 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1572 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
[all …]
DARMInstrInfo.td2536 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2537 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2652 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2655 "ldrd", "\t$Rt, $Rt2, $addr!",
2665 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2668 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2809 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2810 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2975 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2977 "strd", "\t$Rt, $Rt2, $addr!",
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td1122 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1123 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1124 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
1130 bits<4> Rt2;
1136 let Inst{19-16} = Rt2;
1146 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1151 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1152 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
1158 bits<4> Rt2;
1164 let Inst{19-16} = Rt2;
[all …]
DARMInstrThumb2.td1449 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1451 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>,
1631 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1632 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>,
1749 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1751 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1757 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1759 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1764 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1765 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td1191 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1192 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1193 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
1199 bits<4> Rt2;
1205 let Inst{19-16} = Rt2;
1215 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1220 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1221 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
1227 bits<4> Rt2;
1233 let Inst{19-16} = Rt2;
[all …]
DARMInstrThumb2.td1450 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1452 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",
1453 [(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,
1633 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1634 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",
1635 [(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,
1752 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1754 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1760 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1762 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
[all …]
DARMInstrInfo.td2808 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2809 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2932 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2935 "ldrd", "\t$Rt, $Rt2, $addr!",
2945 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2948 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
3092 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
3093 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
3266 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
3268 "strd", "\t$Rt, $Rt2, $addr!",
[all …]
/external/crosvm/sys_util/src/
Dsignal.rs141 Rt2, enumerator
229 2 => Rt2, in try_from()
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.cpp3099 IValueT Rt2 = encodeGPRegister(OpRt2, "Rt", Vmovdrr); in vmovdrr() local
3102 assert(Rt2 != RegARM32::Encoded_Reg_sp); in vmovdrr()
3103 assert(Rt2 != RegARM32::Encoded_Reg_pc); in vmovdrr()
3104 assert(Rt != Rt2); in vmovdrr()
3107 (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) | in vmovdrr()
3150 IValueT Rt2 = encodeGPRegister(OpRt2, "Rt", Vmovrrd); in vmovrrd() local
3154 assert(Rt2 != RegARM32::Encoded_Reg_sp); in vmovrrd()
3155 assert(Rt2 != RegARM32::Encoded_Reg_pc); in vmovrrd()
3156 assert(Rt != Rt2); in vmovrrd()
3159 (encodeCondition(Cond) << kConditionShift) | (Rt2 << 16) | in vmovrrd()
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td3201 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3203 bits<5> Rt2;
3212 let Inst{14-10} = Rt2;
3223 (outs regtype:$Rt, regtype:$Rt2),
3227 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3228 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3237 (ins regtype:$Rt, regtype:$Rt2,
3242 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3243 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3250 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
[all …]

123