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Searched refs:ST0 (Results 1 – 25 of 65) sorted by relevance

123

/external/mesa3d/src/mesa/x86/
Dx86_xform4.S120 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
124 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
136 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
138 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
139 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
140 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
152 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
154 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
[all …]
Dx86_xform3.S120 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
124 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
136 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
138 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
139 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
140 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
223 FADDP( ST0, ST(4) ) /* F1 F2 F5 F4 */
224 FADDP( ST0, ST(2) ) /* F2 F5 F4 */
[all …]
Dx86_xform2.S120 FADDP( ST0, ST(7) ) /* F2 F1 F3 F7 F6 F5 F4 */
122 FADDP( ST0, ST(5) ) /* F2 F3 F7 F6 F5 F4 */
123 FADDP( ST0, ST(3) ) /* F3 F7 F6 F5 F4 */
124 FADDP( ST0, ST(1) ) /* F7 F6 F5 F4 */
273 FADDP( ST0, ST(5) ) /* F1 F2 F6 F5 F4 */
274 FADDP( ST0, ST(3) ) /* F2 F6 F5 F4 */
275 FADDP( ST0, ST(1) ) /* F6 F5 F4 */
353 FADDP( ST0, ST(2) ) /* F4 F5 */
421 FADDP( ST0, ST(3) ) /* F1 F5 F4 */
422 FADDP( ST0, ST(1) ) /* F5 F4 */
[all …]
Dx86_cliptest.S229 FMUL2( ST(1), ST0 )
232 FMUL2( ST(2), ST0 )
235 FMUL2( ST(3), ST0 )
/external/python/cpython2/Lib/test/
Dallsans.pem10 ST0/px0zmKsYgmH8KkhfH7MNfeX9rLCpPJuXA/eo2G03tzGEPqqwQhxsb2ygv2Qs
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/X86/
DTargetTest.cpp297 EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)), in TEST_F()
317 EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)), in TEST_F()
326 EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)), in TEST_F()
/external/llvm-project/llvm/lib/Target/X86/
DX86InsertWait.cpp61 (Reg >= X86::ST0 && Reg <= X86::ST7)); in isX87Reg()
DX86FloatingPoint.cpp205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
852 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1111 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true)); in handleZeroArgFP()
1157 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true)); in handleOneArgFP()
1652 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
DX86Instr3DNow.td78 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
/external/llvm/test/CodeGen/X86/
Dipra-reg-usage.ll6 …P4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0 ST1 ST2 ST3 ST4 ST5…
Dinline-asm-fpstack.ll349 …es:frndint> [sideeffect] [attdialect], $0:[regdef], %ST0<imp-def,tied5>, $1:[reguse tiedto:$0], %S…
351 ; %FP0<def> = COPY %ST0
/external/llvm-project/llvm/test/DebugInfo/COFF/
Dfp-stack.ll15 ; OBJ: Register: ST0 (0x80)
/external/llvm-project/mlir/test/Dialect/Linalg/
Dbufferize.mlir201 // CHECK-SAME: %[[ST0:[0-9a-z]*]]: tensor<2x3xf32>
212 // CHECK-DAG: %[[SM0:.*]] = tensor_to_memref %[[ST0]] : memref<2x3xf32>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FloatingPoint.cpp205 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
852 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1111 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true)); in handleZeroArgFP()
1157 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true)); in handleOneArgFP()
1649 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
DX86Instr3DNow.td78 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7] in
DX86RegisterInfo.cpp573 Reserved.set(X86::ST0 + n); in getReservedRegs()
/external/llvm/lib/Target/X86/
DX86FloatingPoint.cpp197 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
483 MBB->addLiveIn(X86::ST0+i-1); in setupBlockStack()
805 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); in popStackAfter()
1583 Op.setReg(X86::ST0 + FPReg); in handleSpecialFP()
DX86RegisterInfo.cpp478 Reserved.set(X86::ST0 + n); in getReservedRegs()
DX86RegisterInfo.td151 // MMX Registers. These are actually aliased to ST0 .. ST7
242 def ST0 : X86Reg<"st(0)", 0>, DwarfRegNum<[33, 12, 11]>;
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV4.td152 // ST0
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86ATTInstPrinter.cpp484 if (Reg == X86::ST0) in printSTiRegOperand()
DX86IntelInstPrinter.cpp441 if (Reg == X86::ST0) in printSTiRegOperand()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86ATTInstPrinter.cpp494 if (Reg == X86::ST0) in printSTiRegOperand()
DX86IntelInstPrinter.cpp450 if (Reg == X86::ST0) in printSTiRegOperand()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc155 ST0 = 135,
1271 { X86::ST0 },
2396 X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
2748 { 33U, X86::ST0 },
2801 { 12U, X86::ST0 },
2846 { 11U, X86::ST0 },
2915 { 33U, X86::ST0 },
2968 { 12U, X86::ST0 },
3013 { 11U, X86::ST0 },
3091 { X86::ST0, 33U },
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