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/external/llvm-project/llvm/test/CodeGen/ARM/
Dfpconv.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
3 ; RUN: llc -mtriple=armv8r-none-none-eabi %s -o - | FileCheck %s --check-prefix=CHECK-VFP
4 … llc -mtriple=armv8r-none-none-eabi -mattr=-fp64 %s -o - | FileCheck %s --check-prefix=CHECK-VFP-SP
7 ;CHECK-VFP-LABEL: f1:
8 ;CHECK-VFP: vcvt.f32.f64
9 ;CHECK-VFP-SP-LABEL: f1:
10 ;CHECK-VFP-SP: bl __aeabi_d2f
19 ;CHECK-VFP-LABEL: f2:
20 ;CHECK-VFP: vcvt.f64.f32
21 ;CHECK-VFP-SP-LABEL: f2:
[all …]
Dfp16-promote.ll1 …w-deprecated-dag-overlap %s -check-prefix=CHECK-FP16 --check-prefix=CHECK-VFP -check-prefix=CHECK…
2 …eck-prefix=CHECK-LIBCALL --check-prefix=CHECK-VFP -check-prefix=CHECK-ALL --check-prefix=CHECK-LIB…
13 ; CHECK-VFP: vadd.f32
30 ; CHECK-VFP: vsub.f32
47 ; CHECK-VFP: vmul.f32
64 ; CHECK-VFP: vdiv.f32
122 ; CHECK-VFP-NEXT: vmov.f32 s2, s0
123 ; CHECK-VFP-NEXT: vmov.f32 s0, s1
124 ; CHECK-VFP-NEXT: vmov.f32 s1, s2
137 ; CHECK-VFP-NEXT: vmov.f32 s2, s0
[all …]
Dfpvcvtr.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
2 ; RUN: llc -mtriple=thumbv7-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
11 ; CHECK-VFP: vcvtr.s32.f32 s0, s0
18 ; CHECK-VFP: vcvtr.u32.f32 s0, s0
25 ; CHECK-VFP: vcvtr.s32.f64 s0, d{{.*}}
32 ; CHECK-VFP: vcvtr.u32.f64 s0, d{{.*}}
Dno-fpu.ll4 …N: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,+vfp2 | FileCheck --check-prefix=NONEON-VFP %s
22 ; Likewise with VFP instructions.
29 ; NONEON-VFP: vmov
30 ; NONEON-VFP: vmul.f64
Dinlineasm-X-allocation.ll2 …iple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefixes=COMMON,VFP
16 ; VFP: FOO s0, s0
Dselect.ll4 ; RUN: | FileCheck %s --check-prefix=CHECK-VFP
67 ;CHECK-VFP-LABEL: f7:
68 ;CHECK-VFP: vmovmi
101 ; CHECK-VFP-LABEL: f9:
D2013-04-16-AAPCS-C5-vs-VFP.ll7 ;Co-Processor register candidates may be either in VFP or in stack, so after
8 ;all VFP are allocated, stack is used. We can use stack without GPR allocation
Dvector-extend-narrow.ll23 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
52 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
/external/llvm/test/MC/ARM/
Dvfp-aliases-diagnostics.s34 @ CHECK: error: VFP/Neon double precision register expected
37 @ CHECK: error: VFP/Neon double precision register expected
40 @ CHECK: error: VFP/Neon double precision register expected
43 @ CHECK: error: VFP/Neon double precision register expected
46 @ CHECK: error: VFP/Neon single precision register expected
49 @ CHECK: error: VFP/Neon single precision register expected
52 @ CHECK: error: VFP/Neon single precision register expected
55 @ CHECK: error: VFP/Neon single precision register expected
59 @ CHECK: error: VFP/Neon single precision register expected
62 @ CHECK: error: VFP/Neon single precision register expected
[all …]
Dsingle-precision-fp.s10 @ CHECK-ERRORS: error: instruction requires: double precision VFP
12 @ CHECK-ERRORS: error: instruction requires: double precision VFP
14 @ CHECK-ERRORS: error: instruction requires: double precision VFP
16 @ CHECK-ERRORS: error: instruction requires: double precision VFP
18 @ CHECK-ERRORS: error: instruction requires: double precision VFP
29 @ CHECK-ERRORS: error: instruction requires: double precision VFP
31 @ CHECK-ERRORS: error: instruction requires: double precision VFP
33 @ CHECK-ERRORS: error: instruction requires: double precision VFP
35 @ CHECK-ERRORS: error: instruction requires: double precision VFP
37 @ CHECK-ERRORS: error: instruction requires: double precision VFP
[all …]
Dneon-mov-vfp.s1 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
2 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
14 @ VFP-DAG: error: instruction requires: NEON
15 @ VFP-DAG: error: instruction requires: NEON
26 @ VFP-DAG: error: instruction requires: NEON
27 @ VFP-DAG: error: instruction requires: NEON
/external/llvm/test/CodeGen/ARM/
Dfpconv.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
5 ;CHECK-VFP-LABEL: f1:
6 ;CHECK-VFP: vcvt.f32.f64
15 ;CHECK-VFP-LABEL: f2:
16 ;CHECK-VFP: vcvt.f64.f32
25 ;CHECK-VFP-LABEL: f3:
26 ;CHECK-VFP: vcvt.s32.f32
35 ;CHECK-VFP-LABEL: f4:
36 ;CHECK-VFP: vcvt.u32.f32
45 ;CHECK-VFP-LABEL: f5:
[all …]
Dfp16-promote.ll1 …=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 --check-prefix=CHECK-VFP -check-prefix=CHECK…
2 …eck-prefix=CHECK-LIBCALL --check-prefix=CHECK-VFP -check-prefix=CHECK-ALL --check-prefix=CHECK-LIB…
13 ; CHECK-VFP: vadd.f32
30 ; CHECK-VFP: vsub.f32
47 ; CHECK-VFP: vmul.f32
64 ; CHECK-VFP: vdiv.f32
122 ; CHECK-VFP-NEXT: vmov.f32 s2, s0
123 ; CHECK-VFP-NEXT: vmov.f32 s0, s1
124 ; CHECK-VFP-NEXT: vmov.f32 s1, s2
137 ; CHECK-VFP-NEXT: vmov.f32 s2, s0
[all …]
Dno-fpu.ll4 …N: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,+vfp2 | FileCheck --check-prefix=NONEON-VFP %s
22 ; Likewise with VFP instructions.
29 ; NONEON-VFP: vmov
30 ; NONEON-VFP: vmul.f64
Dselect.ll4 ; RUN: | FileCheck %s --check-prefix=CHECK-VFP
67 ;CHECK-VFP-LABEL: f7:
68 ;CHECK-VFP: vmovmi
101 ; CHECK-VFP-LABEL: f9:
D2013-04-16-AAPCS-C5-vs-VFP.ll7 ;Co-Processor register candidates may be either in VFP or in stack, so after
8 ;all VFP are allocated, stack is used. We can use stack without GPR allocation
Dvector-extend-narrow.ll23 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
52 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
/external/llvm-project/llvm/test/MC/ARM/
Dsingle-precision-fp.s10 @ CHECK-ERRORS: error: instruction requires: double precision VFP
12 @ CHECK-ERRORS: error: instruction requires: double precision VFP
14 @ CHECK-ERRORS: error: instruction requires: double precision VFP
16 @ CHECK-ERRORS: error: instruction requires: double precision VFP
18 @ CHECK-ERRORS: error: instruction requires: double precision VFP
29 @ CHECK-ERRORS: error: instruction requires: double precision VFP
31 @ CHECK-ERRORS: error: instruction requires: double precision VFP
33 @ CHECK-ERRORS: error: instruction requires: double precision VFP
35 @ CHECK-ERRORS: error: instruction requires: double precision VFP
37 @ CHECK-ERRORS: error: instruction requires: double precision VFP
[all …]
Dneon-mov-vfp.s1 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
2 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
14 @ VFP-DAG: error: instruction requires: NEON
15 @ VFP-DAG: error: instruction requires: NEON
26 @ VFP-DAG: error: instruction requires: NEON
27 @ VFP-DAG: error: instruction requires: NEON
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
10 // This file describes the ARM VFP instruction set.
108 // Some single precision VFP instructions may be executed on both NEON and VFP
127 // Some single precision VFP instructions may be executed on both NEON and VFP
180 // Some single precision VFP instructions may be executed on both NEON and
181 // VFP pipelines.
193 // Some single precision VFP instructions may be executed on both NEON and
194 // VFP pipelines.
206 // Some single precision VFP instructions may be executed on both NEON and
207 // VFP pipelines.
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
9 // This file describes the ARM VFP instruction set.
153 // Some single precision VFP instructions may be executed on both NEON and VFP
175 // Some single precision VFP instructions may be executed on both NEON and VFP
230 // Some single precision VFP instructions may be executed on both NEON and
231 // VFP pipelines.
243 // Some single precision VFP instructions may be executed on both NEON and
244 // VFP pipelines.
256 // Some single precision VFP instructions may be executed on both NEON and
257 // VFP pipelines.
[all …]
DARM.td36 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
41 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
204 // Cyclone can zero VFP registers in 0 cycles.
251 "Use a wide stride when allocating VFP registers">;
259 // VFP register widths.
262 "Splat register from VFP to NEON",
265 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
268 "Expand VFP/NEON MLA/MLS instructions">;
270 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
275 // VFP to NEON, as an execution domain optimization.
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
9 // This file describes the ARM VFP instruction set.
163 // Some single precision VFP instructions may be executed on both NEON and VFP
198 // Some single precision VFP instructions may be executed on both NEON and VFP
266 // Some single precision VFP instructions may be executed on both NEON and
267 // VFP pipelines.
279 // Some single precision VFP instructions may be executed on both NEON and
280 // VFP pipelines.
292 // Some single precision VFP instructions may be executed on both NEON and
293 // VFP pipelines.
[all …]
DARM.td36 // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only
41 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
204 // Cyclone can zero VFP registers in 0 cycles.
251 "Use a wide stride when allocating VFP registers">;
259 // VFP register widths.
262 "Splat register from VFP to NEON",
265 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
268 "Expand VFP/NEON MLA/MLS instructions">;
270 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
275 // VFP to NEON, as an execution domain optimization.
[all …]
/external/vixl/src/aarch32/
Doperands-aarch32.h524 if (VFP::IsImmFP32(imm)) { in ImmediateVFP()
525 SetEncodingValue(VFP::FP32ToImm8(imm)); in ImmediateVFP()
529 if (VFP::IsImmFP64(imm)) { in ImmediateVFP()
530 SetEncodingValue(VFP::FP64ToImm8(imm)); in ImmediateVFP()
541 return VFP::Imm8ToFP32(imm8); in Decode()
545 return VFP::Imm8ToFP64(imm8); in Decode()

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