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Searched refs:VMOVRRD (Results 1 – 25 of 47) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/ARM/
Dpeephole-phi.mir19 …; CHECK: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[DEF]], 14 /* CC::al */, $…
26 ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[VMOVRRD]], %bb.1, [[VMOVRS]], %bb.2
33 %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg
Dsingle-issue-r52.mir29 # CHECK: SU(3): %5:gpr, %6:gpr = VMOVRRD %4:dpr, 14, $noreg
81 %5, %6 = VMOVRRD %4, 14, $noreg
Dcortex-a57-misched-vfma.ll71 ; > VMLAfd not-optimized latency to VMOVRRD = 9
148 ; > VMLSfd not-optimized latency to VMOVRRD = 9
Dvector-DAGCombine.ll38 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dpredicated-invariant.mir102 ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
103 …; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, i…
152 renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
153 … renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit $q1
Dlivereg-no-loop-def.mir114 ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
115 …; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, i…
164 renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14, $noreg
165 renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14, $noreg, implicit $q0
Dinvariant-qreg.mir182 ; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
183 …; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, i…
231 renamable $r0, renamable $r1 = VMOVRRD renamable $d0, 14 /* CC::al */, $noreg
232 … renamable $r2, renamable $r3 = VMOVRRD killed renamable $d1, 14 /* CC::al */, $noreg, implicit $q0
/external/llvm-project/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp26 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp189 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMInstructionSelector.cpp288 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
935 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD)) in select()
DARMISelLowering.h112 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp1651 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
2198 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
3045 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
3067 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
3136 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
4979 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
4981 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
5805 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
5821 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
6004 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
[all …]
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp192 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMISelLowering.h76 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp1151 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
1552 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
2305 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2327 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2395 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
3701 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
3703 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
4300 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4316 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
4487 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
[all …]
DARMISelDAGToDAG.cpp442 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasNoVMLxHazardUse()
2893 case ARMISD::VMOVRRD: in Select()
2894 ReplaceNode(N, CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32, in Select()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp26 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DMLxExpansionPass.cpp189 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) in hasRAWHazard()
DARMInstructionSelector.cpp290 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
937 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(ARM::VMOVRRD)) in select()
DARMISelLowering.h110 VMOVRRD, // double to two gprs. enumerator
DARMISelLowering.cpp1589 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; in getTargetNodeName()
2062 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in PassF64ArgInRegs()
2827 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2849 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, in LowerReturn()
2918 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) { in isUsedByReturnOnly()
4701 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
4703 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl, in getCMOV()
5558 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
5574 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
5815 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, in ExpandBITCAST()
[all …]
DARMInstrVFP.td27 def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>;
1121 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
2624 (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>;
/external/llvm-project/llvm/test/CodeGen/ARM/GlobalISel/
Dselect-fp.mir69 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr, [[UNINTERESTING:%[0-9]+]]:gpr = VMOVRRD [[VREG]]
861 ; CHECK: [[OUT1:%[0-9]+]]:gpr, [[OUT2:%[0-9]+]]:gpr = VMOVRRD %[[DREG]]
/external/llvm/test/CodeGen/ARM/
Dvector-DAGCombine.ll38 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is

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