Searched refs:fldcw (Results 1 – 25 of 65) sorted by relevance
123
19 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)21 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)33 ; X64-X87-NEXT: fldcw -{{[0-9]+}}(%rsp)35 ; X64-X87-NEXT: fldcw -{{[0-9]+}}(%rsp)59 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)61 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)73 ; X64-X87-NEXT: fldcw -{{[0-9]+}}(%rsp)75 ; X64-X87-NEXT: fldcw -{{[0-9]+}}(%rsp)99 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)101 ; X86-NEXT: fldcw (%esp)[all …]
242 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)244 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)258 ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)260 ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)279 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)281 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)295 ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)297 ; X64-NEXT: fldcw -{{[0-9]+}}(%rsp)316 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)318 ; X86-NEXT: fldcw {{[0-9]+}}(%esp)[all …]
12 ; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)14 ; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)24 ; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)27 ; CHECK-NEXT: fldcw -{{[0-9]+}}(%rsp)
110 ; X87-WIN-NEXT: fldcw {{[0-9]+}}(%esp)112 ; X87-WIN-NEXT: fldcw {{[0-9]+}}(%esp)126 ; X87-LIN-NEXT: fldcw {{[0-9]+}}(%esp)128 ; X87-LIN-NEXT: fldcw {{[0-9]+}}(%esp)165 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)167 ; X87-NEXT: fldcw (%esp)242 ; X86-SSE1-WIN-NEXT: fldcw {{[0-9]+}}(%esp)244 ; X86-SSE1-WIN-NEXT: fldcw {{[0-9]+}}(%esp)258 ; X86-SSE1-LIN-NEXT: fldcw {{[0-9]+}}(%esp)260 ; X86-SSE1-LIN-NEXT: fldcw {{[0-9]+}}(%esp)[all …]
67 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)69 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)114 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)116 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)161 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)163 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)204 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)206 ; X87-NEXT: fldcw (%esp)234 ; SSE-X86-NEXT: fldcw {{[0-9]+}}(%esp)236 ; SSE-X86-NEXT: fldcw {{[0-9]+}}(%esp)[all …]
22 ; SSE2-NEXT: fldcw -8(%rbp)24 ; SSE2-NEXT: fldcw -4(%rbp)35 ; SSE2-NEXT: fldcw -6(%rbp)38 ; SSE2-NEXT: fldcw -2(%rbp)61 ; SSE2-SCHEDULE-NEXT: fldcw -8(%rbp)63 ; SSE2-SCHEDULE-NEXT: fldcw -4(%rbp)74 ; SSE2-SCHEDULE-NEXT: fldcw -6(%rbp)77 ; SSE2-SCHEDULE-NEXT: fldcw -2(%rbp)
16 ; precision6-NEXT: fldcw {{[0-9]+}}(%esp)18 ; precision6-NEXT: fldcw (%esp)44 ; precision12-NEXT: fldcw {{[0-9]+}}(%esp)46 ; precision12-NEXT: fldcw (%esp)74 ; precision18-NEXT: fldcw {{[0-9]+}}(%esp)76 ; precision18-NEXT: fldcw (%esp)118 ; precision6-NEXT: fldcw {{[0-9]+}}(%esp)120 ; precision6-NEXT: fldcw (%esp)145 ; precision12-NEXT: fldcw {{[0-9]+}}(%esp)147 ; precision12-NEXT: fldcw (%esp)[all …]
190 ; X86-SSE2-WIN-NEXT: fldcw {{[0-9]+}}(%esp)192 ; X86-SSE2-WIN-NEXT: fldcw {{[0-9]+}}(%esp)219 ; X86-SSE2-LIN-NEXT: fldcw {{[0-9]+}}(%esp)221 ; X86-SSE2-LIN-NEXT: fldcw {{[0-9]+}}(%esp)255 ; X87-WIN-NEXT: fldcw {{[0-9]+}}(%esp)257 ; X87-WIN-NEXT: fldcw {{[0-9]+}}(%esp)289 ; X87-LIN-NEXT: fldcw {{[0-9]+}}(%esp)291 ; X87-LIN-NEXT: fldcw {{[0-9]+}}(%esp)399 ; X86-SSE2-WIN-NEXT: fldcw {{[0-9]+}}(%esp)401 ; X86-SSE2-WIN-NEXT: fldcw {{[0-9]+}}(%esp)[all …]
57 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)59 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)72 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)74 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
90 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)92 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
62 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)64 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)71 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)73 ; SSE-32-NEXT: fldcw (%esp)242 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)244 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)260 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)262 ; SSE-32-NEXT: fldcw (%esp)540 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)542 ; SSE-32-NEXT: fldcw {{[0-9]+}}(%esp)[all …]
110 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)112 ; CHECK-NEXT: fldcw (%esp)
432 ; INLINEASM $fldcw $0 [sideeffect] [mayload] [attdialect], $0:[mem], undef %eax, 1, %noreg, 0, %nor…455 ; CHECK-NEXT: fldcw (%eax)462 ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)464 ; CHECK-NEXT: fldcw (%esp)479 call void asm sideeffect "fldcw $0", "*m,~{dirflag},~{fpsr},~{flags}"(i32* undef)
935 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)937 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)982 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)984 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)1027 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)1029 ; X87-NEXT: fldcw (%esp)1070 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)1072 ; X87-NEXT: fldcw {{[0-9]+}}(%esp)1091 ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)1093 ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)[all …]
952 fldcw 485498096 label956 fldcw 64(%rdx) label960 fldcw -64(%rdx,%rax,4) label964 fldcw 64(%rdx,%rax,4) label968 fldcw 64(%rdx,%rax) label972 fldcw (%rdx) label
952 fldcw -485498096(%edx,%eax,4) label956 fldcw 485498096(%edx,%eax,4) label960 fldcw 485498096(%edx) label964 fldcw 485498096 label968 fldcw 64(%edx,%eax) label972 fldcw (%edx) label
174 __asm fldcw word ptr [mask]\180 __asm fldcw word ptr [mask]\185 __asm fldcw word ptr [x]\
21 fldcw [rsp]
29 fldcw [rsp]
198 __asm { fldcw cw } in Force64BitFPUPrecision()
350 ; INLINEASM <es:fldcw $0> [sideeffect] [mayload] [attdialect], $0:[mem], %EAX<undef>, 1, %noreg, 0,…358 ; CHECK: fldcw376 call void asm sideeffect "fldcw $0", "*m,~{dirflag},~{fpsr},~{flags}"(i32* undef)
98 fldcw (%eax) label282 # CHECK-NEXT: 1 5 2.50 * U fldcw (%eax)441 # CHECK-NEXT: 2.50 2.50 fldcw (%eax)
98 fldcw (%eax) label282 # CHECK-NEXT: 5 8 2.00 * U fldcw (%eax)447 # CHECK-NEXT: - - - - 1.00 2.00 1.00 1.00 fldcw (%eax)
98 fldcw (%eax) label282 # CHECK-NEXT: 3 7 1.00 * U fldcw (%eax)449 # CHECK-NEXT: - - 1.50 - 0.50 0.50 - 0.50 - - fldcw (%eax)
98 fldcw (%eax) label282 # CHECK-NEXT: 3 7 1.00 * U fldcw (%eax)449 # CHECK-NEXT: - - 1.50 0.50 0.50 0.50 - - - - fldcw (%eax)