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Searched refs:lsll (Results 1 – 16 of 16) sorted by relevance

/external/llvm-project/llvm/test/MC/X86/
DI286-32.s85 lsll 3809469200(%edx,%eax,4), %eax label
89 lsll 485498096, %eax label
93 lsll 485498096(%edx,%eax,4), %eax label
97 lsll 485498096(%edx), %eax label
101 lsll 64(%edx,%eax), %eax label
105 lsll %eax, %eax label
109 lsll (%edx), %eax label
DI286-64.s149 lsll 485498096, %r13d label
153 lsll 64(%rdx), %r13d label
157 lsll 64(%rdx,%rax,4), %r13d label
161 lsll -64(%rdx,%rax,4), %r13d label
165 lsll 64(%rdx,%rax), %r13d label
169 lsll %r13d, %r13d label
173 lsll (%rdx), %r13d label
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dlongshift-const.ll5 declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32)
126 ; CHECK-NEXT: lsll r0, r1, #2
145 ; CHECK-NEXT: lsll r0, r1, #32
212 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 0)
225 ; CHECK-NEXT: lsll r0, r1, #23
231 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 23)
244 ; CHECK-NEXT: lsll r0, r1, #32
250 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 32)
264 ; CHECK-NEXT: lsll r0, r1, r2
270 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 33)
[all …]
Dlongshift-demand.ll5 declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32)
30 ; CHECK-NEXT: lsll r0, r1, #3
36 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 3)
50 ; CHECK-NEXT: lsll r0, r1, #3
76 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 -3)
111 ; CHECK-NEXT: lsll r0, r1, #31
117 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 31)
131 ; CHECK-NEXT: lsll r0, r1, #31
157 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 -31)
192 ; CHECK-NEXT: lsll r0, r1, #32
[all …]
Dscalar-shifts.ll28 ; CHECK-NEXT: lsll r0, r1, r2
34 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 %shift)
44 declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32)
/external/llvm-project/llvm/test/MC/ARM/
Dmve-scalar-shift.s94 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21]
96 lsll lr, r1, #11 label
98 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
100 lsll lr, r1, r4 label
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-shifts.ll40 ; CHECK-NEXT: lsll r2, r1, r0
46 ; CHECK-NEXT: lsll r2, r1, r0
97 ; CHECK-NEXT: lsll r0, r1, r2
104 ; CHECK-NEXT: lsll r0, r1, r2
206 ; CHECK-NEXT: lsll r0, r1, #4
211 ; CHECK-NEXT: lsll r0, r1, #4
365 ; CHECK-NEXT: lsll r2, r1, r0
370 ; CHECK-NEXT: lsll r2, r1, r0
428 ; CHECK-NEXT: lsll r2, r1, r0
433 ; CHECK-NEXT: lsll r2, r1, r0
Dshift_parts.ll8 ; CHECK-MVE-NEXT: lsll r0, r1, r2
32 ; CHECK-MVE-NEXT: lsll r0, r1, #3
83 ; CHECK-MVE-NEXT: lsll r0, r1, r2
203 ; CHECK-MVE-NEXT: lsll r2, r1, #8
/external/llvm-project/clang/test/CodeGen/arm-mve-intrinsics/
Dscalar-shifts.c41 return lsll(value, shift); in test_lsll()
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-scalar-shift.txt18 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21]
22 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
/external/llvm-project/clang/include/clang/Basic/
Darm_mve.td1271 def lsll: LongScalarShift<u64, (args s32:$sh), (IRInt<"lsll"> $lo, $hi, $sh)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td540 def MVE_LSLLr : MVE_ScalarShiftDRegReg<"lsll", 0b0, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
543 def MVE_LSLLi : MVE_ScalarShiftDRegImm<"lsll", 0b00, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrMVE.td580 def MVE_LSLLr : MVE_ScalarShiftDRegReg<"lsll", 0b0, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
583 def MVE_LSLLi : MVE_ScalarShiftDRegImm<"lsll", 0b00, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9891 "l\004lsll\003lsr\004lsrl\003mcr\004mcr2\004mcrr\005mcrr2\003mla\003mls\003"
10761 …{ 645 /* lsll */, ARM::MVE_LSLLr, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__Reg1_3__CondCode2_0…
10762 …{ 645 /* lsll */, ARM::MVE_LSLLi, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__MVELongShift1_3__Co…
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenAsmMatcher.inc7695 "\006loopne\005lretl\005lretq\005lretw\003lsl\004lsll\004lslq\004lslw\003"
9101 { 4149 /* lsll */, X86::LSL32rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR32, MCK_GR32 }, },
9102 …{ 4149 /* lsll */, X86::LSL32rm, Convert__Reg1_1__Mem165_0, AMFBS_None, { MCK_Mem16, MCK_GR32 }, },
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc1581 "llvm.arm.mve.lsll",
11714 1, // llvm.arm.mve.lsll