Home
last modified time | relevance | path

Searched refs:lzcnt (Results 1 – 25 of 93) sorted by relevance

1234

/external/llvm-project/clang/include/clang/Basic/
DX86Target.def93 …mov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2")
95 …mov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2")
96 …mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
98 …mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
99 …e,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+ad…
101 …sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx,+mpx")
102 …e,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+a…
103 …e,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+a…
104 …e,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+ad…
/external/llvm/test/CodeGen/X86/
Dlzcnt-tzcnt.ll1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+bmi,+lzcnt | FileCheck %s
16 ; CHECK: lzcnt
27 ; CHECK: lzcnt
38 ; CHECK: lzcnt
49 ; CHECK: lzcnt
60 ; CHECK: lzcnt
71 ; CHECK: lzcnt
84 ; CHECK: lzcnt
97 ; CHECK: lzcnt
110 ; CHECK: lzcnt
[all …]
Davx512cdvl-intrinsics.ll6 declare <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32>, <4 x i32>, i8)
18 %res = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
19 %res1 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1)
20 …%res3 = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer,…
26 declare <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32>, <8 x i32>, i8)
36 %res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
37 %res1 = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1)
42 declare <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64>, <2 x i64>, i8)
52 %res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
53 %res1 = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1)
[all …]
/external/llvm-project/llvm/test/tools/llvm-mca/X86/Barcelona/
Dpartial-reg-update-6.s4 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
6 # The last lzcnt has a false dependency on %cx. However, even in this case, the
10 lzcnt (%rsp), %cx label
11 lzcnt 2(%rsp), %cx label
Dpartial-reg-update-4.s4 # The lzcnt cannot execute in parallel with the imul because there is a false
8 lzcnt %ax, %bx label
Dclear-super-register-1.s9 lzcnt %ecx, %eax label
Dpartial-reg-update-2.s5 lzcnt %ax, %bx label
/external/llvm-project/llvm/test/tools/llvm-mca/X86/BtVer2/
Dpartial-reg-update-6.s5 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
7 # The last lzcnt has a false dependency on %cx. However, even in this case, the
11 lzcnt (%rsp), %cx label
12 lzcnt 2(%rsp), %cx label
Dpartial-reg-update-4.s6 # The lzcnt cannot execute in parallel with the imul because there is a false
10 lzcnt %ax, %bx label
Dclear-super-register-1.s9 lzcnt %ecx, %eax label
/external/llvm-project/llvm/test/tools/llvm-mca/X86/Znver1/
Dpartial-reg-update-6.s4 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
6 # The last lzcnt has a false dependency on %cx. However, even in this case, the
10 lzcnt (%rsp), %cx label
11 lzcnt 2(%rsp), %cx label
Dpartial-reg-update-4.s4 # The lzcnt cannot execute in parallel with the imul because there is a false
8 lzcnt %ax, %bx label
/external/llvm-project/llvm/test/tools/llvm-mca/X86/Znver2/
Dpartial-reg-update-6.s4 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
6 # The last lzcnt has a false dependency on %cx. However, even in this case, the
10 lzcnt (%rsp), %cx label
11 lzcnt 2(%rsp), %cx label
Dpartial-reg-update-4.s4 # The lzcnt cannot execute in parallel with the imul because there is a false
8 lzcnt %ax, %bx label
/external/llvm-project/llvm/test/tools/llvm-mca/X86/BdVer2/
Dpartial-reg-update-6.s5 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
7 # The last lzcnt has a false dependency on %cx. However, even in this case, the
11 lzcnt (%rsp), %cx label
12 lzcnt 2(%rsp), %cx label
Dpartial-reg-update-4.s6 # The lzcnt cannot execute in parallel with the imul because there is a false
10 lzcnt %ax, %bx label
Dclear-super-register-1.s9 lzcnt %ecx, %eax label
/external/llvm-project/llvm/test/CodeGen/X86/
Davx512cdvl-intrinsics-upgrade.ll5 declare <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32>, <4 x i32>, i8)
12 %res = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 -1)
31 %res = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> %x1, i8 %x2)
48 …%res = call <4 x i32> @llvm.x86.avx512.mask.lzcnt.d.128(<4 x i32> %x0, <4 x i32> zeroinitializer, …
52 declare <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32>, <8 x i32>, i8)
59 %res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 -1)
78 %res = call <8 x i32> @llvm.x86.avx512.mask.lzcnt.d.256(<8 x i32> %x0, <8 x i32> %x1, i8 %x2)
82 declare <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64>, <2 x i64>, i8)
89 %res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 -1)
108 %res = call <2 x i64> @llvm.x86.avx512.mask.lzcnt.q.128(<2 x i64> %x0, <2 x i64> %x1, i8 %x2)
[all …]
Davx512cd-intrinsics-upgrade.ll102 …%res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> zeroinitializer…
106 declare <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
113 …%res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i…
117 declare <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
134 %res = call <16 x i32> @llvm.x86.avx512.mask.lzcnt.d.512(<16 x i32> %a, <16 x i32> %b, i16 %mask)
153 %res = call <8 x i64> @llvm.x86.avx512.mask.lzcnt.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
Dlzcnt-zext-cmp.ll2 ; Test patterns which generates lzcnt instructions.
3 ; Eg: zext(or(setcc(cmp), setcc(cmp))) -> shr(or(lzcnt, lzcnt))
5 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=btver2 -mattr=-fast-lzcnt | FileCheck --check-prefix…
7 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver1 -mattr=-fast-lzcnt | FileCheck --check-prefix…
9 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=znver2 -mattr=-fast-lzcnt | FileCheck --check-prefix…
Dpr35399.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=lzcnt | FileCheck %s
Dlzcnt.ll2 ; RUN: llc < %s -mtriple=i686-- -mattr=+lzcnt | FileCheck %s --check-prefix=X86
3 ; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+lzcnt | FileCheck %s --check-prefix=X32
4 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+lzcnt | FileCheck %s --check-prefix=X64
Dvector-width-store-merge.ll70 …i,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmu…
72 …i,+bmi2,+clflushopt,+clwb,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmu…
/external/llvm-project/polly/test/ScopInfo/
Ddo-not-model-error-block-accesses.ll27 …="+aes,+avx,+avx2,+bmi,+bmi2,+cmov,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+hle,+lzcnt,+mmx,+movbe,+pclmu…
28 …="+aes,+avx,+avx2,+bmi,+bmi2,+cmov,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+hle,+lzcnt,+mmx,+movbe,+pclmu…
/external/llvm-project/llvm/test/Transforms/LoopVectorize/X86/
Dint128_no_gather.ll74 …,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+…
75 …,+avx512vl,+bmi,+bmi2,+clflushopt,+clwb,+cx16,+f16c,+fma,+fsgsbase,+fxsr,+lzcnt,+mmx,+movbe,+mpx,+…

1234