| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_cp_reg_shadowing.c | 30 static void si_build_load_reg(struct si_screen *sscreen, struct si_pm4_state *pm4, in si_build_load_reg() argument
59 si_pm4_cmd_add(pm4, PKT3(packet, 1 + num_ranges * 2, 0)); in si_build_load_reg()
60 si_pm4_cmd_add(pm4, gpu_address); in si_build_load_reg()
61 si_pm4_cmd_add(pm4, gpu_address >> 32); in si_build_load_reg()
63 si_pm4_cmd_add(pm4, (ranges[i].offset - offset) / 4); in si_build_load_reg()
64 si_pm4_cmd_add(pm4, ranges[i].size / 4); in si_build_load_reg()
71 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); in si_create_shadowing_ib_preamble() local
75 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
76 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0)); in si_create_shadowing_ib_preamble()
80 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0)); in si_create_shadowing_ib_preamble()
[all …]
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| D | si_state_shaders.c | 325 struct si_pm4_state *pm4) in si_set_tesseval_regs() argument
382 assert(pm4->shader); in si_set_tesseval_regs()
383 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) | in si_set_tesseval_regs()
403 struct si_shader *shader, struct si_pm4_state *pm4) in polaris_set_vgt_vertex_reuse() argument
419 assert(pm4->shader); in polaris_set_vgt_vertex_reuse()
420 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth; in polaris_set_vgt_vertex_reuse()
426 if (shader->pm4) in si_get_shader_pm4_state()
427 si_pm4_clear_state(shader->pm4); in si_get_shader_pm4_state()
429 shader->pm4 = CALLOC_STRUCT(si_pm4_state); in si_get_shader_pm4_state()
431 if (shader->pm4) { in si_get_shader_pm4_state()
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| D | si_state.c | 435 struct si_pm4_state *pm4 = &blend->pm4; in si_create_blend_state_mode() local
459 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
465 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
501 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
511 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
521 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
577 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
613 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]); in si_create_blend_state_mode()
620 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); in si_create_blend_state_mode()
825 struct si_pm4_state *pm4 = &rs->pm4; in si_create_rs_state() local
[all …]
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| D | si_pm4.c | 40 state->pm4[state->ndw++] = dw; in si_pm4_cmd_add()
48 state->pm4[state->last_pm4] = PKT3(state->last_opcode, count, predicate); in si_pm4_cmd_end()
84 state->pm4[state->ndw++] = reg; in si_pm4_set_reg()
88 state->pm4[state->ndw++] = val; in si_pm4_set_reg()
119 radeon_emit_array(cs, state->pm4, state->ndw); in si_pm4_emit()
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| D | si_pm4.h | 50 uint32_t pm4[SI_PM4_MAX_DW]; member
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| D | si_state.h | 50 struct si_pm4_state pm4; member
67 struct si_pm4_state pm4; member
123 struct si_pm4_state pm4; member
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| D | si_shader.h | 726 struct si_pm4_state *pm4; member
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| D | si_debug.c | 415 ac_parse_ib(f, ctx->cs_preamble_state->pm4, ctx->cs_preamble_state->ndw, NULL, 0, in si_log_chunk_type_cs_print()
419 ac_parse_ib(f, ctx->cs_preamble_gs_rings->pm4, ctx->cs_preamble_gs_rings->ndw, NULL, 0, in si_log_chunk_type_cs_print()
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| /external/igt-gpu-tools/tests/amdgpu/ |
| D | amd_basic.c | 856 uint32_t *pm4; in amdgpu_command_submission_write_linear_helper() local
869 pm4 = calloc(pm4_dw, sizeof(*pm4)); in amdgpu_command_submission_write_linear_helper()
870 igt_assert(pm4); in amdgpu_command_submission_write_linear_helper()
904 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, in amdgpu_command_submission_write_linear_helper()
906 pm4[i++] = 0xffffffff & bo_mc; in amdgpu_command_submission_write_linear_helper()
907 pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; in amdgpu_command_submission_write_linear_helper()
909 pm4[i++] = sdma_write_length - 1; in amdgpu_command_submission_write_linear_helper()
911 pm4[i++] = sdma_write_length; in amdgpu_command_submission_write_linear_helper()
913 pm4[i++] = 0xdeadbeaf; in amdgpu_command_submission_write_linear_helper()
916 pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); in amdgpu_command_submission_write_linear_helper()
[all …]
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| /external/libdrm/tests/amdgpu/ |
| D | basic_tests.c | 896 uint32_t *pm4; in amdgpu_bo_eviction_test() local
906 pm4 = calloc(pm4_dw, sizeof(*pm4)); in amdgpu_bo_eviction_test()
907 CU_ASSERT_NOT_EQUAL(pm4, NULL); in amdgpu_bo_eviction_test()
982 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, in amdgpu_bo_eviction_test()
984 pm4[i++] = 0xffffffff & bo2_mc; in amdgpu_bo_eviction_test()
985 pm4[i++] = 0xffffffff & bo1_mc; in amdgpu_bo_eviction_test()
986 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; in amdgpu_bo_eviction_test()
987 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; in amdgpu_bo_eviction_test()
989 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); in amdgpu_bo_eviction_test()
991 pm4[i++] = sdma_write_length - 1; in amdgpu_bo_eviction_test()
[all …]
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| /external/ltp/testcases/kernel/mem/mem/ |
| D | mem02.c | 77 char *pm1, *pm2, *pm3, *pm4; in main() local
159 pm4 = pm3 = malloc(10); in main()
161 *pm4++ = 'X'; in main()
164 pm4 = realloc(pm3, 5); in main()
165 pm3 = pm4; in main()
168 if (*pm4++ != 'X') { in main()
177 pm4 = realloc(pm3, 15); in main()
178 pm3 = pm4; in main()
188 free(pm4); in main()
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| /external/mesa3d/src/freedreno/registers/adreno/ |
| D | meson.build | 66 'adreno-pm4-pack.xml.h',
68 output: 'adreno-pm4-pack.xml.h',
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| /external/mesa3d/src/freedreno/ |
| D | Android.registers.mk | 52 …h a5xx.xml.h a6xx.xml.h a6xx-pack.xml.h adreno_common.xml.h adreno_pm4.xml.h adreno-pm4-pack.xml.h)
94 $(intermediates)/registers/adreno/adreno-pm4-pack.xml.h: $(LOCAL_PATH)/registers/adreno/adreno_pm4.…
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| /external/clang/test/CXX/temp/temp.arg/temp.arg.nontype/ |
| D | p1-11.cpp | 43 PM<(int X::*)0> pm4; variable
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| /external/llvm-project/clang/test/CXX/temp/temp.arg/temp.arg.nontype/ |
| D | p1-11.cpp | 43 PM<(int X::*)0> pm4; variable
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| /external/mesa3d/src/freedreno/vulkan/ |
| D | msm_kgsl.h | 373 unsigned int pm4; member
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| /external/mesa3d/docs/relnotes/ |
| D | 20.2.0.rst | 3447 - freedreno: android: add adreno-pm4-pack.xml.h generation to android build
|