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Searched refs:v1024i1 (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td304 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
305 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
308 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
309 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
312 def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))),
313 (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>,
316 def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))),
317 (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
320 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
321 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>,
[all …]
DHexagonIntrinsicsV60.td46 def : Pat <(v1024i1 (bitconvert (v32i32 HvxVR:$src1))),
47 (v1024i1 (V6_vandvrt (v32i32 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
49 def : Pat <(v1024i1 (bitconvert (v64i16 HvxVR:$src1))),
50 (v1024i1 (V6_vandvrt (v64i16 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
52 def : Pat <(v1024i1 (bitconvert (v128i8 HvxVR:$src1))),
53 (v1024i1 (V6_vandvrt (v128i8 HvxVR:$src1), (A2_tfrsi 0x01010101)))>;
55 def : Pat <(v32i32 (bitconvert (v1024i1 HvxQR:$src1))),
56 (v32i32 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
58 def : Pat <(v64i16 (bitconvert (v1024i1 HvxQR:$src1))),
59 (v64i16 (V6_vandqrt (v1024i1 HvxQR:$src1), (A2_tfrsi 0x01010101)))>;
[all …]
DHexagonRegisterInfo.td286 [v512i1, v1024i1, v512i1]>;
DHexagonISelDAGToDAGHVX.cpp2213 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
2227 SDVTList VTs = CurDAG->getVTList(MVT::v32i32, MVT::v1024i1); in SelectHVXDualOutput()
DHexagonISelLoweringHVX.cpp53 addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass); in initializeHVXLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV60.td124 def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
125 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
129 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
130 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
134 def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
135 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
139 def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
140 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
144 def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
145 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
[all …]
DHexagonISelLowering.cpp204 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) { in CC_Hexagon_VarArg()
372 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { in CC_HexagonVector()
420 (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) { in RetCC_Hexagon()
549 ty == MVT::v512i1 || ty == MVT::v1024i1); in IsHvxVectorType()
1146 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) { in LowerFormalArguments()
1773 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass); in HexagonTargetLowering()
2871 case MVT::v1024i1: in getRegForInlineAsmConstraint()
DHexagonRegisterInfo.td244 def VecPredRegs128B : RegisterClass<"Hexagon", [v1024i1], 1024,
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h66 v1024i1 = 20, // 1024 x i1 enumerator
272 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
324 case v1024i1: return i1; in getVectorElementType()
375 case v1024i1: return 1024; in getVectorNumElements()
503 case v1024i1: in getSizeInBits()
600 if (NumElements == 1024) return MVT::v1024i1; in getVectorVT()
DValueTypes.td43 def v1024i1: ValueType<1024,20>; //1024 x i1 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h70 v1024i1 = 24, // 1024 x i1 enumerator
375 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
438 case v1024i1: in getVectorElementType()
553 case v1024i1: in getVectorNumElements()
803 case v1024i1: in getSizeInBits()
933 if (NumElements == 1024) return MVT::v1024i1; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h71 v1024i1 = 25, // 1024 x i1 enumerator
408 return (SimpleTy == MVT::v1024i1 || SimpleTy == MVT::v128i8 || in is1024BitVector()
505 case v1024i1: in getVectorElementType()
646 case v1024i1: in getVectorNumElements()
942 case v1024i1: in getSizeInBits()
1120 if (NumElements == 1024) return MVT::v1024i1; in getVectorVT()
/external/llvm/lib/IR/
DValueTypes.cpp152 case MVT::v1024i1: return "v1024i1"; in getEVTString()
230 case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp80 case MVT::v1024i1: return "MVT::v1024i1"; in getEnumName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp169 case MVT::v1024i1: return VectorType::get(Type::getInt1Ty(Context), 1024); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td45 def v1024i1: ValueType<1024,24>; //1024 x i1 vector value
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td47 def v1024i1: ValueType<1024,25>; //1024 x i1 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp218 case MVT::v1024i1: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp91 case MVT::v1024i1: return "MVT::v1024i1"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td176 def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td236 def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsics.td267 def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1