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Searched refs:v4i1 (Results 1 – 25 of 261) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-pred-constfold.ll84 %l5 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l4)
149 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1)
150 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
152 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
154 %9 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 65534)
155 %10 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %9)
157 %12 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %9)
176 %4 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 1)
177 %5 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %0, i32 0, <4 x i1> %4)
179 %7 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %1, i32 0, <4 x i1> %4)
[all …]
Dmve-vpt-blocks.ll4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
28 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
29 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x …
43 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
44 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
45 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
60 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
61 …%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
62 …%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
[all …]
Dcde-vec.ll118 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
121 declare <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 immarg, <4 x i32>, <16 x i8>, i32 i…
122 declare <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, …
123 declare <2 x i64> @llvm.arm.cde.vcx3q.predicated.v2i64.v4i1(i32 immarg, <2 x i64>, <16 x i8>, <16 x…
124 declare <4 x float> @llvm.arm.cde.vcx3qa.predicated.v4f32.v4i1(i32 immarg, <4 x float>, <16 x i8>, …
164 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
165 …%3 = call <4 x i32> @llvm.arm.cde.vcx2q.predicated.v4i32.v4i1(i32 0, <4 x i32> %inactive, <16 x i8…
179 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
180 …%3 = call <4 x float> @llvm.arm.cde.vcx2qa.predicated.v4f32.v4i1(i32 0, <4 x float> %acc, <16 x i8…
194 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/ARM/
Dmve-v2i2v.ll6 declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
10 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
23 %int = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
24 %vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %int)
56 ; CHECK-NEXT: [[INT:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> [[VIN:%.*]]), !range !0
61 %int = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vin)
70 ; CHECK-NEXT: [[VOUT:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[INT]])
75 %vout = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %int)
101 %vec = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %iin)
102 %iout = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %vec)
[all …]
/external/llvm-project/llvm/test/Analysis/Lint/
Dget-active-lane-mask.ll6 ; CHECK-NEXT: %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
8 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 0)
17 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 1)
26 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 -1)
35 %res = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 %IV, i32 %TC)
39 declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvrint-predicated.ll27 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
28 …%2 = tail call <4 x float> @llvm.arm.mve.vrinta.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1,…
55 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
56 …%2 = tail call <4 x float> @llvm.arm.mve.vrintm.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1,…
83 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
84 …%2 = tail call <4 x float> @llvm.arm.mve.vrintn.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1,…
111 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
112 …%2 = tail call <4 x float> @llvm.arm.mve.vrintp.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1,…
139 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
140 …%2 = tail call <4 x float> @llvm.arm.mve.vrintz.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1,…
[all …]
Dvqdmull.ll4 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
8 declare <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x…
9 declare <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x…
41 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
42 …%2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, …
55 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
56 …%2 = call <2 x i64> @llvm.arm.mve.vqdmull.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, …
96 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
97 …%2 = call <4 x i32> @llvm.arm.mve.vqdmull.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %.sp…
112 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
[all …]
Dvcvt-fp-int.ll41 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
42 …%2 = tail call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %a, i32…
55 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
56 …%2 = tail call <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32> %a, i32…
83 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
84 …%2 = tail call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %a, i32…
111 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
112 …%2 = tail call <4 x i32> @llvm.arm.mve.vcvt.fp.int.predicated.v4i32.v4f32.v4i1(<4 x float> %a, i32…
117 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
120 declare <4 x float> @llvm.arm.mve.vcvt.fp.int.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>,…
[all …]
Dabsneg-predicated.ll42 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
43 …%2 = tail call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i…
84 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
85 …%2 = tail call <4 x i32> @llvm.arm.mve.mvn.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i…
112 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
113 …%2 = tail call <4 x float> @llvm.arm.mve.neg.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4…
154 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
155 …%2 = tail call <4 x i32> @llvm.arm.mve.neg.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i…
182 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
183 …%2 = tail call <4 x float> @llvm.arm.mve.abs.predicated.v4f32.v4i1(<4 x float> %a, <4 x i1> %1, <4…
[all …]
Dscatter-gather.ll105 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
106 …%2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0i8.v4i32.v4i1(i8* %base, <…
110 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
112 declare <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0i8.v4i32.v4i1(i8*, <4 x i32>,…
158 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
159 …%2 = call <4 x i32> @llvm.arm.mve.vldr.gather.offset.predicated.v4i32.p0i8.v4i32.v4i1(i8* %base, <…
248 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
249 …%3 = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v4i1(<…
256 declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v4i1(<2 x…
270 %2 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
[all …]
Dvmullbq.ll80 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
81 …%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16…
85 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
87 declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32…
98 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
99 …%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32…
103 declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32…
144 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
145 …%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16…
159 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
[all …]
Dvcvt_anpm.ll187 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
188 …%2 = tail call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactiv…
215 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
216 …%2 = tail call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> %inactiv…
243 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
244 …%2 = tail call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactiv…
271 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
272 …%2 = tail call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> %inactiv…
299 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
300 …%2 = tail call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> %inactiv…
[all …]
Dvadc.ll59 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
60 …%2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4…
69 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
71 declare { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>…
90 %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
91 …%4 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vadc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4…
184 declare { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i32>…
198 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
199 …%2 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vsbc.predicated.v4i32.v4i1(<4 x i32> %inactive, <4…
220 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
[all …]
Dvcvt.ll4 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
17 declare <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32, <4 x float>, <4 x i32>,…
19 declare <4 x i32> @llvm.arm.mve.vcvt.fix.predicated.v4i32.v4f32.v4i1(i32, <4 x i32>, <4 x float>, i…
50 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
64 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
186 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
187 …%2 = call <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32 0, <4 x float> %inact…
200 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
201 …%2 = call <4 x float> @llvm.arm.mve.vcvt.fix.predicated.v4f32.v4i32.v4i1(i32 1, <4 x float> %inact…
242 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
[all …]
Dvclzcls-predicated.ll41 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
42 …%2 = tail call <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i…
83 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
84 …%2 = tail call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i…
125 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
126 …%2 = tail call <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i1> %1, <4 x i…
132 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
135 declare <4 x i32> @llvm.arm.mve.cls.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)
138 declare <4 x i32> @llvm.arm.mve.clz.predicated.v4i32.v4i1(<4 x i32>, <4 x i1>, <4 x i32>)
Dvcmulq.ll5 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
11 declare <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32, <4 x float>, <4 x float>, <4 x …
120 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
121 …%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 0, <4 x float> %inactive, <4 …
148 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
149 …%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 1, <4 x float> %inactive, <4 …
176 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
177 …%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 2, <4 x float> %inactive, <4 …
204 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
205 …%2 = call <4 x float> @llvm.arm.mve.vcmulq.predicated.v4f32.v4i1(i32 3, <4 x float> %inactive, <4 …
[all …]
Dvaddv.ll167 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
168 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %a, i32 0, <4 x i1> %1)
209 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
210 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %a, i32 1, <4 x i1> %1)
253 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
254 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %b, i32 0, <4 x i1> %1)
298 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
299 %2 = tail call i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32> %b, i32 1, <4 x i1> %1)
355 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
356 %2 = tail call i64 @llvm.arm.mve.addlv.predicated.v4i32.v4i1(<4 x i32> %a, i32 0, <4 x i1> %1)
[all …]
Dvmulltq.ll80 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
81 …%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16…
85 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
87 declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32…
98 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
99 …%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32…
103 declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32…
144 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
145 …%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16…
159 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
[all …]
Dpredicates.ll9 declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
13 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
87 %1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %0)
102 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
105 %4 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %3)
118 %1 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %0)
133 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
136 %4 = call i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1> %3)
188 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
201 %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
[all …]
Dvector-shift-imm.ll131 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
132 …%2 = tail call <4 x i32> @llvm.arm.mve.shl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 0, <4 x i1>…
173 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
174 …%2 = tail call <4 x i32> @llvm.arm.mve.shr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 13, i32 0, …
215 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
216 …%2 = tail call <4 x i32> @llvm.arm.mve.shr.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 21, i32 1, …
257 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
258 …%2 = tail call <4 x i32> @llvm.arm.mve.shl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 13, <4 x i1…
299 %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
300 …%2 = tail call <4 x i32> @llvm.arm.mve.shl.imm.predicated.v4i32.v4i1(<4 x i32> %a, i32 30, <4 x i1…
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td230 [(set v4f64:$FRT, (vselect v4i1:$FRA,
236 [(set v4f32:$FRT, (vselect v4i1:$FRA,
242 [(set v4i1:$FRT, (vselect v4i1:$FRA,
243 v4i1:$FRC, v4i1:$FRB))]>;
269 [(set v4i1:$dst,
270 (select i1:$cond, v4i1:$T, v4i1:$F))]>;
346 [/* (set v4i1:$FRT, v4i1:$FRB) */]>;
402 [(set v4i1:$FRT,
403 (PPCqvaligni v4i1:$FRA, v4i1:$FRB,
421 [(set v4i1:$FRT,
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td231 [(set v4f64:$FRT, (vselect v4i1:$FRA,
237 [(set v4f32:$FRT, (vselect v4i1:$FRA,
243 [(set v4i1:$FRT, (vselect v4i1:$FRA,
244 v4i1:$FRC, v4i1:$FRB))]>;
271 [(set v4i1:$dst,
272 (select i1:$cond, v4i1:$T, v4i1:$F))]>;
349 [/* (set v4i1:$FRT, v4i1:$FRB) */]>;
405 [(set v4i1:$FRT,
406 (PPCqvaligni v4i1:$FRA, v4i1:$FRB,
424 [(set v4i1:$FRT,
[all …]
/external/swiftshader/third_party/subzero/crosstest/
Dtest_select_main.cpp70 void testSelect<v4f32, v4i1>(size_t &TotalTests, size_t &Passes, in testSelect()
96 std::cout << vectAsString<v4i1>(Cond) in testSelect()
140 testSelect<v4f32, v4i1>(TotalTests, Passes, Failures); in main()
141 testSelect<v4si32, v4i1>(TotalTests, Passes, Failures); in main()
142 testSelect<v4ui32, v4i1>(TotalTests, Passes, Failures); in main()
147 testSelectI1<v4i1>(TotalTests, Passes, Failures); in main()
/external/swiftshader/third_party/subzero/src/
DIceTypes.def47 X(v4i1, 4, 1, 4, i1, "<4 x i1>", "v4i1") \
75 X(v4i1, 1, 1, 0, 0, 1, 1, v4i1) \
80 X(v4i32, 1, 1, 0, 1, 0, 1, v4i1) \
81 X(v4f32, 1, 0, 1, 0, 0, 1, v4i1) \
/external/llvm-project/llvm/test/Transforms/LoopStrengthReduce/ARM/
Dvctp-chains.ll23 …at>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> [[TMP14]]…
26 ; CHECK-NEXT: [[TMP19]] = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x flo…
52 …at>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %14, i32 …
55 …%19 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %13, <4 x float> %…
84 …at>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> [[TMP14]]…
87 ; CHECK-NEXT: [[TMP19]] = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x flo…
113 …at>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %14, i32 …
116 …%19 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %13, <4 x float> %…
144 …at>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> [[TMP14]]…
147 ; CHECK-NEXT: [[TMP19]] = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x flo…
[all …]

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