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Searched refs:v64i32 (Results 1 – 25 of 35) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dctpop-split.ll9 %t0 = call <64 x i16> @llvm.ctpop.v64i32(<64 x i16> %a0)
21 declare <64 x i16> @llvm.ctpop.v64i32(<64 x i16>) #0
Disel-split-masked.ll11 …%v0 = call <64 x i32> @llvm.masked.load.v64i32.p0v64i32(<64 x i32>* nonnull undef, i32 4, <64 x i1…
25 declare <64 x i32> @llvm.masked.load.v64i32.p0v64i32(<64 x i32>*, i32 immarg, <64 x i1>, <64 x i32>…
Dwiden-ext.ll42 ; v64i8 -> v64i32
Dwiden-trunc.ll47 ; v64i32 -> v64i8
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h93 v64i32 = 44, // 64 x i32 enumerator
280 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
348 case v64i32: return i32; in getVectorElementType()
383 case v64i32: return 64; in getVectorNumElements()
510 case v64i32: in getSizeInBits()
630 if (NumElements == 64) return MVT::v64i32; in getVectorVT()
DValueTypes.td70 def v64i32 : ValueType<2048,44>; // 32 x i32 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td102 CCIfType<[v64i32,v128i16,v256i8],
108 CCIfType<[v64i32,v128i16,v256i8],
128 CCIfType<[v64i32,v128i16,v256i8],
DHexagonIntrinsics.td271 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
272 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>,
275 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
276 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>,
350 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
DHexagonIntrinsicsV60.td21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
635 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonCallingConv.td132 CCIfType<[v64i32,v128i16,v256i8],
138 CCIfType<[v64i32,v128i16,v256i8],
158 CCIfType<[v64i32,v128i16,v256i8],
DHexagonIntrinsics.td273 def : Pat <(v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
274 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo))>,
277 def : Pat <(v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
278 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi))>,
282 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
DHexagonIntrinsicsV60.td21 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 HvxWR:$src1))),
22 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_lo)) >;
24 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 HvxWR:$src1))),
25 (v32i32 (EXTRACT_SUBREG (v64i32 HvxWR:$src1), vsub_hi)) >;
635 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h100 v64i32 = 51, // 64 x i32 enumerator
383 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
483 case v64i32: in getVectorElementType()
571 case v64i32: in getVectorNumElements()
813 case v64i32: in getSizeInBits()
966 if (NumElements == 64) return MVT::v64i32; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h101 v64i32 = 52, // 64 x i32 enumerator
418 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 || in is2048BitVector()
552 case v64i32: in getVectorElementType()
670 case v64i32: in getVectorNumElements()
955 case v64i32: in getSizeInBits()
1153 if (NumElements == 64) return MVT::v64i32; in getVectorVT()
/external/llvm/lib/IR/
DValueTypes.cpp176 case MVT::v64i32: return "v64i32"; in getEVTString()
254 case MVT::v64i32: return VectorType::get(Type::getInt32Ty(Context), 64); in getTypeForEVT()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
425 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { in RetCC_Hexagon()
426 LocVT = MVT::v64i32; in RetCC_Hexagon()
427 ValVT = MVT::v64i32; in RetCC_Hexagon()
439 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) { in RetCC_Hexagon()
497 } else if (LocVT == MVT::v64i32) { in RetCC_HexagonVector()
547 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1140 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || in LowerFormalArguments()
1771 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
[all …]
DHexagonIntrinsicsV60.td73 def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
74 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
78 def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
79 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1),
832 def: Pat<(v64i16 (trunc v64i32:$Vdd)),
DHexagonRegisterInfo.td238 [v256i8,v128i16,v64i32,v32i64], 2048,
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-int-reduce.ll251 %res = call i32 @llvm.vector.reduce.add.v64i32(<64 x i32> %op)
559 %res = call i32 @llvm.vector.reduce.smax.v64i32(<64 x i32> %op)
869 %res = call i32 @llvm.vector.reduce.smin.v64i32(<64 x i32> %op)
1179 %res = call i32 @llvm.vector.reduce.umax.v64i32(<64 x i32> %op)
1489 %res = call i32 @llvm.vector.reduce.umin.v64i32(<64 x i32> %op)
1592 declare i32 @llvm.vector.reduce.add.v64i32(<64 x i32>)
1620 declare i32 @llvm.vector.reduce.smax.v64i32(<64 x i32>)
1648 declare i32 @llvm.vector.reduce.smin.v64i32(<64 x i32>)
1676 declare i32 @llvm.vector.reduce.umax.v64i32(<64 x i32>)
1704 declare i32 @llvm.vector.reduce.umin.v64i32(<64 x i32>)
Dsve-fixed-length-log-reduce.ll264 %res = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %op)
587 %res = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %op)
910 %res = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %op)
1013 declare i32 @llvm.vector.reduce.and.v64i32(<64 x i32>)
1041 declare i32 @llvm.vector.reduce.or.v64i32(<64 x i32>)
1069 declare i32 @llvm.vector.reduce.xor.v64i32(<64 x i32>)
Dsve-fixed-length-int-minmax.ll297 %res = call <64 x i32> @llvm.smax.v64i32(<64 x i32> %op1, <64 x i32> %op2)
669 %res = call <64 x i32> @llvm.smin.v64i32(<64 x i32> %op1, <64 x i32> %op2)
1042 %res = call <64 x i32> @llvm.umax.v64i32(<64 x i32> %op1, <64 x i32> %op2)
1414 %res = call <64 x i32> @llvm.umin.v64i32(<64 x i32> %op1, <64 x i32> %op2)
1532 declare <64 x i32> @llvm.smin.v64i32(<64 x i32>, <64 x i32>)
1557 declare <64 x i32> @llvm.smax.v64i32(<64 x i32>, <64 x i32>)
1582 declare <64 x i32> @llvm.umin.v64i32(<64 x i32>, <64 x i32>)
1607 declare <64 x i32> @llvm.umax.v64i32(<64 x i32>, <64 x i32>)
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp104 case MVT::v64i32: return "MVT::v64i32"; in getEnumName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp196 case MVT::v64i32: return VectorType::get(Type::getInt32Ty(Context), 64); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td75 def v64i32 : ValueType<2048,51>; // 64 x i32 vector value
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td77 def v64i32 : ValueType<2048,52>; // 64 x i32 vector value

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