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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
3
4define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) {
5; CHECK-LABEL: main:
6; CHECK:       ; %bb.0: ; %main_body
7; CHECK-NEXT:    CALL_FS
8; CHECK-NEXT:    ALU 24, @12, KC0[CB0:0-32], KC1[]
9; CHECK-NEXT:    EXPORT T0.XYZW
10; CHECK-NEXT:    EXPORT T0.0000
11; CHECK-NEXT:    EXPORT T0.0000
12; CHECK-NEXT:    EXPORT T4.0YZW
13; CHECK-NEXT:    EXPORT T3.XYZW
14; CHECK-NEXT:    EXPORT T2.XY00
15; CHECK-NEXT:    EXPORT T0.0000
16; CHECK-NEXT:    EXPORT T0.0000
17; CHECK-NEXT:    CF_END
18; CHECK-NEXT:    PAD
19; CHECK-NEXT:    ALU clause starting at 12:
20; CHECK-NEXT:     MUL_IEEE * T0.W, KC0[4].X, T1.X,
21; CHECK-NEXT:     MULADD_IEEE T0.W, KC0[5].X, T1.Y, PV.W,
22; CHECK-NEXT:     MUL_IEEE * T2.W, KC0[4].Y, T1.X,
23; CHECK-NEXT:     MULADD_IEEE * T0.W, KC0[6].X, T1.Z, PV.W,
24; CHECK-NEXT:     MULADD_IEEE T0.X, KC0[7].X, T1.W, PV.W,
25; CHECK-NEXT:     MULADD_IEEE * T0.W, KC0[5].Y, T1.Y, T2.W,
26; CHECK-NEXT:     MUL_IEEE * T2.W, KC0[4].Z, T1.X,
27; CHECK-NEXT:     MOV T2.Y, KC0[2].Z,
28; CHECK-NEXT:     MULADD_IEEE * T2.W, KC0[5].Z, T1.Y, PV.W,
29; CHECK-NEXT:     MULADD_IEEE * T0.W, KC0[6].Y, T1.Z, T0.W,
30; CHECK-NEXT:     MOV T2.X, KC0[2].Y,
31; CHECK-NEXT:     MULADD_IEEE * T0.Y, KC0[7].Y, T1.W, PV.W,
32; CHECK-NEXT:     MULADD_IEEE * T0.W, KC0[6].Z, T1.Z, T2.W,
33; CHECK-NEXT:     MULADD_IEEE T0.Z, KC0[7].Z, T1.W, PV.W,
34; CHECK-NEXT:     MUL_IEEE * T0.W, KC0[4].W, T1.X,
35; CHECK-NEXT:     MOV * T3.W, KC0[2].X,
36; CHECK-NEXT:     MOV T3.Z, KC0[3].Z,
37; CHECK-NEXT:     MULADD_IEEE * T0.W, KC0[5].W, T1.Y, T0.W,
38; CHECK-NEXT:     MOV * T4.W, KC0[0].Z,
39; CHECK-NEXT:     MOV T3.Y, KC0[3].Y,
40; CHECK-NEXT:     MOV * T4.Z, KC0[0].Y,
41; CHECK-NEXT:     MULADD_IEEE * T0.W, KC0[6].W, T1.Z, T0.W,
42; CHECK-NEXT:     MOV T3.X, KC0[3].X,
43; CHECK-NEXT:     MOV * T4.Y, KC0[0].X,
44; CHECK-NEXT:     MULADD_IEEE * T0.W, KC0[7].W, T1.W, T0.W,
45main_body:
46  %0 = extractelement <4 x float> %reg1, i32 0
47  %1 = extractelement <4 x float> %reg1, i32 1
48  %2 = extractelement <4 x float> %reg1, i32 2
49  %3 = extractelement <4 x float> %reg1, i32 3
50  %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
51  %5 = extractelement <4 x float> %4, i32 0
52  %6 = fmul float %5, %0
53  %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
54  %8 = extractelement <4 x float> %7, i32 1
55  %9 = fmul float %8, %0
56  %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
57  %11 = extractelement <4 x float> %10, i32 2
58  %12 = fmul float %11, %0
59  %13 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4)
60  %14 = extractelement <4 x float> %13, i32 3
61  %15 = fmul float %14, %0
62  %16 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
63  %17 = extractelement <4 x float> %16, i32 0
64  %18 = fmul float %17, %1
65  %19 = fadd float %18, %6
66  %20 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
67  %21 = extractelement <4 x float> %20, i32 1
68  %22 = fmul float %21, %1
69  %23 = fadd float %22, %9
70  %24 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
71  %25 = extractelement <4 x float> %24, i32 2
72  %26 = fmul float %25, %1
73  %27 = fadd float %26, %12
74  %28 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5)
75  %29 = extractelement <4 x float> %28, i32 3
76  %30 = fmul float %29, %1
77  %31 = fadd float %30, %15
78  %32 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
79  %33 = extractelement <4 x float> %32, i32 0
80  %34 = fmul float %33, %2
81  %35 = fadd float %34, %19
82  %36 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
83  %37 = extractelement <4 x float> %36, i32 1
84  %38 = fmul float %37, %2
85  %39 = fadd float %38, %23
86  %40 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
87  %41 = extractelement <4 x float> %40, i32 2
88  %42 = fmul float %41, %2
89  %43 = fadd float %42, %27
90  %44 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6)
91  %45 = extractelement <4 x float> %44, i32 3
92  %46 = fmul float %45, %2
93  %47 = fadd float %46, %31
94  %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
95  %49 = extractelement <4 x float> %48, i32 0
96  %50 = fmul float %49, %3
97  %51 = fadd float %50, %35
98  %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
99  %53 = extractelement <4 x float> %52, i32 1
100  %54 = fmul float %53, %3
101  %55 = fadd float %54, %39
102  %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
103  %57 = extractelement <4 x float> %56, i32 2
104  %58 = fmul float %57, %3
105  %59 = fadd float %58, %43
106  %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7)
107  %61 = extractelement <4 x float> %60, i32 3
108  %62 = fmul float %61, %3
109  %63 = fadd float %62, %47
110  %64 = load <4 x float>, <4 x float> addrspace(8)* null
111  %65 = extractelement <4 x float> %64, i32 0
112  %66 = load <4 x float>, <4 x float> addrspace(8)* null
113  %67 = extractelement <4 x float> %66, i32 1
114  %68 = load <4 x float>, <4 x float> addrspace(8)* null
115  %69 = extractelement <4 x float> %68, i32 2
116  %70 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
117  %71 = extractelement <4 x float> %70, i32 0
118  %72 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
119  %73 = extractelement <4 x float> %72, i32 1
120  %74 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2)
121  %75 = extractelement <4 x float> %74, i32 2
122  %76 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
123  %77 = extractelement <4 x float> %76, i32 0
124  %78 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
125  %79 = extractelement <4 x float> %78, i32 1
126  %80 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3)
127  %81 = extractelement <4 x float> %80, i32 2
128  %82 = insertelement <4 x float> undef, float %51, i32 0
129  %83 = insertelement <4 x float> %82, float %55, i32 1
130  %84 = insertelement <4 x float> %83, float %59, i32 2
131  %85 = insertelement <4 x float> %84, float %63, i32 3
132  call void @llvm.r600.store.swizzle(<4 x float> %85, i32 60, i32 1)
133  %86 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
134  %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 1
135  %88 = insertelement <4 x float> %87, float 0.000000e+00, i32 2
136  %89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3
137  call void @llvm.r600.store.swizzle(<4 x float> %89, i32 0, i32 2)
138  %90 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
139  %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 1
140  %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 2
141  %93 = insertelement <4 x float> %92, float 0.000000e+00, i32 3
142  call void @llvm.r600.store.swizzle(<4 x float> %93, i32 1, i32 2)
143  %94 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
144  %95 = insertelement <4 x float> %94, float %65, i32 1
145  %96 = insertelement <4 x float> %95, float %67, i32 2
146  %97 = insertelement <4 x float> %96, float %69, i32 3
147  call void @llvm.r600.store.swizzle(<4 x float> %97, i32 2, i32 2)
148  %98 = insertelement <4 x float> undef, float %77, i32 0
149  %99 = insertelement <4 x float> %98, float %79, i32 1
150  %100 = insertelement <4 x float> %99, float %81, i32 2
151  %101 = insertelement <4 x float> %100, float %71, i32 3
152  call void @llvm.r600.store.swizzle(<4 x float> %101, i32 3, i32 2)
153  %102 = insertelement <4 x float> undef, float %73, i32 0
154  %103 = insertelement <4 x float> %102, float %75, i32 1
155  %104 = insertelement <4 x float> %103, float 0.000000e+00, i32 2
156  %105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3
157  call void @llvm.r600.store.swizzle(<4 x float> %105, i32 4, i32 2)
158  %106 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
159  %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 1
160  %108 = insertelement <4 x float> %107, float 0.000000e+00, i32 2
161  %109 = insertelement <4 x float> %108, float 0.000000e+00, i32 3
162  call void @llvm.r600.store.swizzle(<4 x float> %109, i32 5, i32 2)
163  %110 = insertelement <4 x float> undef, float 0.000000e+00, i32 0
164  %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 1
165  %112 = insertelement <4 x float> %111, float 0.000000e+00, i32 2
166  %113 = insertelement <4 x float> %112, float 0.000000e+00, i32 3
167  call void @llvm.r600.store.swizzle(<4 x float> %113, i32 6, i32 2)
168  ret void
169}
170
171declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
172