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/external/mesa3d/include/pci_ids/
Di965_pci_ids.h1 CHIPSET(0x29A2, i965, "BW", "Intel(R) 965G")
2 CHIPSET(0x2992, i965, "BW", "Intel(R) 965Q")
3 CHIPSET(0x2982, i965, "BW", "Intel(R) 965G")
4 CHIPSET(0x2972, i965, "BW", "Intel(R) 946GZ")
5 CHIPSET(0x2A02, i965, "CL", "Intel(R) 965GM")
6 CHIPSET(0x2A12, i965, "CL", "Intel(R) 965GME/GLE")
8 CHIPSET(0x2A42, g4x, "CTG", "Mobile Intel® GM45 Express Chipset")
9 CHIPSET(0x2E02, g4x, "ELK", "Intel(R) Integrated Graphics Device")
10 CHIPSET(0x2E12, g4x, "ELK", "Intel(R) Q45/Q43")
11 CHIPSET(0x2E22, g4x, "ELK", "Intel(R) G45/G43")
[all …]
Diris_pci_ids.h1 CHIPSET(0x4c8a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
2 CHIPSET(0x4c8b, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
3 CHIPSET(0x4c8c, rkl_gt05, "RKL GT0.5", "Intel(R) Graphics")
4 CHIPSET(0x4c90, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
5 CHIPSET(0x4c9a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
7 CHIPSET(0x4680, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
8 CHIPSET(0x4681, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
9 CHIPSET(0x4682, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
10 CHIPSET(0x4683, adl_gt05, "ADL-S GT0.5", "Intel(R) Graphics")
11 CHIPSET(0x4690, adl_gt1, "ADL-S GT1", "Intel(R) Graphics")
[all …]
Di915_pci_ids.h1 CHIPSET(0x3577, I830_M, "Intel(R) 830M")
2 CHIPSET(0x2562, 845_G, "Intel(R) 845G")
3 CHIPSET(0x3582, I855_GM, "Intel(R) 852GM/855GM")
4 CHIPSET(0x2572, I865_G, "Intel(R) 865G")
5 CHIPSET(0x2582, I915_G, "Intel(R) 915G")
6 CHIPSET(0x258A, E7221_G, "Intel(R) E7221G (i915)")
7 CHIPSET(0x2592, I915_GM, "Intel(R) 915GM")
8 CHIPSET(0x2772, I945_G, "Intel(R) 945G")
9 CHIPSET(0x27A2, I945_GM, "Intel(R) 945GM")
10 CHIPSET(0x27AE, I945_GME, "Intel(R) 945GME")
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/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.c36 intel_batchbuffer_reset(struct intel_context *intel);
39 intel_batchbuffer_init(struct intel_context *intel) in intel_batchbuffer_init() argument
41 intel_batchbuffer_reset(intel); in intel_batchbuffer_init()
43 intel->batch.cpu_map = malloc(intel->maxBatchSize); in intel_batchbuffer_init()
44 intel->batch.map = intel->batch.cpu_map; in intel_batchbuffer_init()
48 intel_batchbuffer_reset(struct intel_context *intel) in intel_batchbuffer_reset() argument
50 if (intel->batch.last_bo != NULL) { in intel_batchbuffer_reset()
51 drm_intel_bo_unreference(intel->batch.last_bo); in intel_batchbuffer_reset()
52 intel->batch.last_bo = NULL; in intel_batchbuffer_reset()
54 intel->batch.last_bo = intel->batch.bo; in intel_batchbuffer_reset()
[all …]
Dintel_tris.c65 intel_flush_inline_primitive(struct intel_context *intel) in intel_flush_inline_primitive() argument
67 GLuint used = intel->batch.used - intel->prim.start_ptr; in intel_flush_inline_primitive()
69 assert(intel->prim.primitive != ~0); in intel_flush_inline_primitive()
76 intel->batch.map[intel->prim.start_ptr] = in intel_flush_inline_primitive()
77 _3DPRIMITIVE | intel->prim.primitive | (used - 2); in intel_flush_inline_primitive()
82 intel->batch.used = intel->prim.start_ptr; in intel_flush_inline_primitive()
85 intel->prim.primitive = ~0; in intel_flush_inline_primitive()
86 intel->prim.start_ptr = 0; in intel_flush_inline_primitive()
87 intel->prim.flush = 0; in intel_flush_inline_primitive()
90 static void intel_start_inline(struct intel_context *intel, uint32_t prim) in intel_start_inline() argument
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Dintel_context.c63 const char *const i915_vendor_string = "Intel Open Source Technology Center";
76 chipset = "Unknown Intel Chipset"; in i915_get_renderer_string()
87 const struct intel_context *const intel = intel_context(ctx); in intelGetString() local
95 (GLubyte *) i915_get_renderer_string(intel->intelScreen->deviceID); in intelGetString()
107 struct intel_context *intel = intel_context(ctx); in intel_flush_front() local
108 __DRIcontext *driContext = intel->driContext; in intel_flush_front()
110 __DRIscreen *const screen = intel->intelScreen->driScrnPriv; in intel_flush_front()
112 if (intel->front_buffer_dirty && _mesa_is_winsys_fbo(ctx->DrawBuffer)) { in intel_flush_front()
121 intel->front_buffer_dirty = false; in intel_flush_front()
127 intel_update_image_buffers(struct intel_context *intel, __DRIdrawable *drawable);
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Dintel_batchbuffer.h23 void intel_batchbuffer_init(struct intel_context *intel);
24 void intel_batchbuffer_free(struct intel_context *intel);
26 int _intel_batchbuffer_flush(struct intel_context *intel,
29 #define intel_batchbuffer_flush(intel) \ argument
30 _intel_batchbuffer_flush(intel, __FILE__, __LINE__)
38 void intel_batchbuffer_data(struct intel_context *intel,
41 bool intel_batchbuffer_emit_reloc(struct intel_context *intel,
46 bool intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel,
51 void intel_batchbuffer_emit_mi_flush(struct intel_context *intel);
70 intel_batchbuffer_space(struct intel_context *intel) in intel_batchbuffer_space() argument
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Dintel_buffer_objects.c48 intel_bufferobj_alloc_buffer(struct intel_context *intel, in intel_bufferobj_alloc_buffer() argument
51 intel_obj->buffer = drm_intel_bo_alloc(intel->bufmgr, "bufferobj", in intel_bufferobj_alloc_buffer()
123 struct intel_context *intel = intel_context(ctx); in intel_bufferobj_data() local
153 intel_bufferobj_alloc_buffer(intel, intel_obj); in intel_bufferobj_data()
177 struct intel_context *intel = intel_context(ctx); in intel_bufferobj_subdata() local
203 drm_intel_bo_references(intel->batch.bo, intel_obj->buffer); in intel_bufferobj_subdata()
209 intel_bufferobj_alloc_buffer(intel, intel_obj); in intel_bufferobj_subdata()
216 drm_intel_bo_alloc(intel->bufmgr, "subdata temp", size, 64); in intel_bufferobj_subdata()
220 intel_emit_linear_blit(intel, in intel_bufferobj_subdata()
243 struct intel_context *intel = intel_context(ctx); in intel_bufferobj_get_subdata() local
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Di830_vtbl.c46 static bool i830_check_vertex_size(struct intel_context *intel,
53 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \
54 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \
55 intel->vertex_attr_count++; \
61 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \
62 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \
63 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \
64 intel->vertex_attr_count++; \
72 i830_render_prevalidate(struct intel_context *intel) in i830_render_prevalidate() argument
77 i830_render_start(struct intel_context *intel) in i830_render_start() argument
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Di915_vtbl.c52 i915_render_prevalidate(struct intel_context *intel) in i915_render_prevalidate() argument
54 struct i915_context *i915 = i915_context(&intel->ctx); in i915_render_prevalidate()
60 i915_render_start(struct intel_context *intel) in i915_render_start() argument
62 intel_prepare_render(intel); in i915_render_start()
67 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim) in i915_reduced_primitive_state() argument
69 struct i915_context *i915 = i915_context(&intel->ctx); in i915_reduced_primitive_state()
77 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple) in i915_reduced_primitive_state()
86 i915->intel.reduced_primitive = rprim; in i915_reduced_primitive_state()
89 INTEL_FIREVERTICES(intel); in i915_reduced_primitive_state()
101 i915_check_vertex_size(struct intel_context *intel, GLuint expected) in i915_check_vertex_size() argument
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Dintel_render.c109 intelDmaPrimitive(struct intel_context *intel, GLenum prim) in intelDmaPrimitive() argument
113 INTEL_FIREVERTICES(intel); in intelDmaPrimitive()
114 intel->vtbl.reduced_primitive_state(intel, reduced_prim[prim]); in intelDmaPrimitive()
115 intel_set_prim(intel, hw_prim[prim]); in intelDmaPrimitive()
120 static inline GLuint intel_get_vb_max(struct intel_context *intel) in intel_get_vb_max() argument
124 if (intel->intelScreen->no_vbo) { in intel_get_vb_max()
125 ret = intel->batch.bo->size - INTEL_NO_VBO_STATE_RESERVED; in intel_get_vb_max()
128 ret /= (intel->vertex_size * 4); in intel_get_vb_max()
132 static inline GLuint intel_get_current_max(struct intel_context *intel) in intel_get_current_max() argument
136 if (intel->intelScreen->no_vbo) { in intel_get_current_max()
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/external/cpuinfo/test/name/
Dbrand-string.cc18 TEST(BRAND_STRING, intel) { in TEST() argument
20 normalize_brand_string("Genuine Intel(R) CPU @ 2.33GHz\0")); in TEST()
22 normalize_brand_string(" Genuine Intel(R) CPU 3.00GHz\0")); in TEST()
24 normalize_brand_string(" Genuine Intel(R) CPU @ 2.60GHz\0")); in TEST()
26 normalize_brand_string("Genuine Intel(R) CPU 0000 @ 1.73GHz\0")); in TEST()
28 normalize_brand_string(" Genuine Intel(R) CPU @ 728\0MHz\0")); in TEST()
30 normalize_brand_string(" Genuine Intel(R) CPU 3.46GHz\0")); in TEST()
32 normalize_brand_string(" Genuine Intel(R) CPU @ 1.66GHz\0")); in TEST()
34 normalize_brand_string("Genuine Intel(R) CPU 0000 @ 2.40GHz\0")); in TEST()
36 normalize_brand_string("Genuine Intel(R) processor 800MHz\0")); in TEST()
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/external/mesa3d/
Daosp-gen-prebuilt.sh28 python3 src/intel/genxml/gen_zipped_file.py src/broadcom/cle/v3d_packet_v21.xml src/broadcom/cle/v3…
34 python3 src/intel/isl/gen_format_layout.py --csv src/intel/isl/isl_format_layout.csv --out prebuilt…
36 python3 src/intel/genxml/gen_bits_header.py --cpp-guard=GENX_BITS_H \
37 src/intel/genxml/gen4.xml \
38 src/intel/genxml/gen45.xml \
39 src/intel/genxml/gen5.xml \
40 src/intel/genxml/gen6.xml \
41 src/intel/genxml/gen7.xml \
42 src/intel/genxml/gen75.xml \
43 src/intel/genxml/gen8.xml \
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/external/arm-trusted-firmware/plat/intel/soc/agilex/
Dplatform.mk3 # Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
9 -Iplat/intel/soc/agilex/include/ \
10 -Iplat/intel/soc/common/drivers/ \
11 -Iplat/intel/soc/common/include/
27 plat/intel/soc/common/aarch64/platform_common.c \
28 plat/intel/soc/common/aarch64/plat_helpers.S \
29 plat/intel/soc/common/socfpga_delay_timer.c
34 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
42 plat/intel/soc/agilex/bl2_plat_setup.c \
43 plat/intel/soc/agilex/soc/agilex_clock_manager.c \
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/external/arm-trusted-firmware/plat/intel/soc/stratix10/
Dplatform.mk3 # Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
9 -Iplat/intel/soc/stratix10/include/ \
10 -Iplat/intel/soc/common/drivers/ \
11 -Iplat/intel/soc/common/include/
27 plat/intel/soc/common/aarch64/platform_common.c \
28 plat/intel/soc/common/aarch64/plat_helpers.S \
29 plat/intel/soc/common/socfpga_delay_timer.c
34 drivers/intel/soc/stratix10/io/s10_memmap_qspi.c \
42 plat/intel/soc/stratix10/bl2_plat_setup.c \
43 plat/intel/soc/stratix10/soc/s10_clock_manager.c \
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/external/cpuinfo/src/x86/
Disa.c58 * - Intel, AMD: ecx[bit 26] in basic info = XSAVE/XRSTOR instructions supported by a chip. in cpuinfo_x86_detect_isa()
59 * - Intel, AMD: ecx[bit 27] in basic info = XSAVE/XRSTOR instructions enabled by OS. in cpuinfo_x86_detect_isa()
73 * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits of ymm registers in cpuinfo_x86_detect_isa()
74 * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for high 128 bits of ymm registers in cpuinfo_x86_detect_isa()
83 * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits of zmm registers in cpuinfo_x86_detect_isa()
84 * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for bits 128-255 of zmm registers in cpuinfo_x86_detect_isa()
85 * - Intel: XFEATURE_ENABLED_MASK[bit 5] for 8 64-bit OpMask registers (k0-k7) in cpuinfo_x86_detect_isa()
86 * - Intel: XFEATURE_ENABLED_MASK[bit 6] for the high 256 bits of the zmm registers zmm0-zmm15 in cpuinfo_x86_detect_isa()
87 * - Intel: XFEATURE_ENABLED_MASK[bit 7] for the 512-bit zmm registers zmm16-zmm31 in cpuinfo_x86_detect_isa()
96 * - Intel: XFEATURE_ENABLED_MASK[bit 3] for BNDREGS in cpuinfo_x86_detect_isa()
[all …]
/external/angle/src/tests/deqp_support/
Ddeqp_gles2_test_expectations.txt115 // Linux OpenGL Intel
116 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.rasterization.interpolation.basic.lines_wide = FAIL
117 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.rasterization.interpolation.basic.line_strip_wide =…
118 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.rasterization.interpolation.basic.line_loop_wide = …
119 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.rasterization.interpolation.projected.lines_wide = …
120 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.rasterization.interpolation.projected.line_strip_wi…
121 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.rasterization.interpolation.projected.line_loop_wid…
122 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.shaders.texture_functions.vertex.texturecubelod = F…
123 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_…
124 3302 OPENGL INTEL LINUX : dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_linear_…
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_object_purgeable.c2 * Copyright © 2010 Intel Corporation
73 struct intel_texture_object *intel; in intel_texture_object_purgeable() local
78 intel = intel_texture_object(obj); in intel_texture_object_purgeable()
79 if (intel->mt == NULL || intel->mt->bo == NULL) in intel_texture_object_purgeable()
82 return intel_buffer_purgeable(intel->mt->bo); in intel_texture_object_purgeable()
90 struct intel_renderbuffer *intel; in intel_render_object_purgeable() local
95 intel = intel_renderbuffer(obj); in intel_render_object_purgeable()
96 if (intel->mt == NULL) in intel_render_object_purgeable()
99 return intel_buffer_purgeable(intel->mt->bo); in intel_render_object_purgeable()
119 struct intel_buffer_object *intel = intel_buffer_object(obj); in intel_buffer_object_unpurgeable() local
[all …]
/external/licenseclassifier/v2/assets/License/GenericIntel/
Dlicense.txt3 Some or all of this work - Copyright (c) 1999 - 2017, Intel Corp.
8 2.1. This is your license from Intel Corp. under its intellectual property
13 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
15 irrevocable, perpetual, worldwide license under Intel's copyrights in the
16 base code distributed originally by Intel ("Original Intel Code") to copy,
20 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
21 license (with the right to sublicense), under only those claims of Intel
22 patents that are infringed by the Original Intel Code, to make, use, sell,
26 to or modifications of the Original Intel Code. No other license or right
44 directly or indirectly, from Original Intel Code.
[all …]
/external/angle/src/tests/
Dangle_end2end_tests_expectations.txt22 6153 VULKAN WIN INTEL : GLSLTest_ES31.StructAndArrayEqualOperator/* = SKIP
68 6101 WIN OPENGL INTEL : BlitFramebufferTest.OOBWrite/* = SKIP
70 6173 WIN INTEL OPENGL : GLSLTest_ES31.BoolInInterfaceBlocks/* = SKIP
71 6217 WIN INTEL OPENGL : GLSLTest_ES31.StorageBufferBoolVectorPassedToFunctions/* = SKIP
72 7143 WIN INTEL OPENGL : GLSLTest.AliasingFunctionOutParamAndGlobal/* = SKIP
76 7298 WIN INTEL D3D11 : BlitFramebufferTest.Blit3DTo2DArray/* = SKIP
78 7700 WIN INTEL D3D11 : FramebufferTest_ES31.ChangeFBOSizeAndAttachmentsCount/* = SKIP
80 7699 WIN INTEL VULKAN : FramebufferTest_ES31.ChangeFBOSizeAndAttachmentsCount/* = SKIP
81 7699 WIN INTEL VULKAN : FramebufferTest_ES31.ChangeFBOSizeWithNoAttachments/* = SKIP
82 7699 WIN INTEL VULKAN : FramebufferTest_ES31.CreateNoAttachmentFBOWithDifferentSize/* = SKIP
[all …]
/external/cpuinfo/src/x86/cache/
Ddescriptor.c28 …* - Application Note 485: Intel Processor Indentification and CPUID Instruction, May 2012, Order N… in cpuinfo_x86_decode_cache_descriptor()
29 …* - Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2 (2A, 2B, 2C & 2D): Inst… in cpuinfo_x86_decode_cache_descriptor()
37 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
50 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
63 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
76 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
89 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
102 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
117 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
132 * Intel ISA Reference: in cpuinfo_x86_decode_cache_descriptor()
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/external/autotest/client/cros/video/detectors/
Dintel_cpu.py12 'Intel(R) Celeron(R) 2955U @ 1.40GHz' : 'intel_celeron_2955U',
13 'Intel(R) Celeron(R) 2957U @ 1.40GHz' : 'intel_celeron_2957U',
14 'Intel(R) Celeron(R) CPU 1007U @ 1.50GHz' : 'intel_celeron_1007U',
15 'Intel(R) Celeron(R) CPU 847 @ 1.10GHz' : 'intel_celeron_847',
16 'Intel(R) Celeron(R) CPU 867 @ 1.30GHz' : 'intel_celeron_867',
17 'Intel(R) Celeron(R) CPU 877 @ 1.40GHz' : 'intel_celeron_877',
18 'Intel(R) Celeron(R) CPU B840 @ 1.90GHz' : 'intel_celeron_B840',
19 'Intel(R) Core(TM) i3-4005U CPU @ 1.70GHz': 'intel_i3_4005U',
20 'Intel(R) Core(TM) i3-4010U CPU @ 1.70GHz': 'intel_i3_4010U',
21 'Intel(R) Core(TM) i3-4030U CPU @ 1.90GHz': 'intel_i3_4030U',
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/external/tensorflow/tensorflow/tools/dockerfiles/partials/onednn/redhat/
Dcpu.partial.Dockerfile4 LABEL name="Intel® Optimizations for TensorFlow*" \
5 maintainer="Abolfazl Shahbazi <abolfazl.shahbazi@intel.com>" \
6 vendor="Intel&#174; Corporation" \
9 …summary="Intel&#174; Optimizations for TensorFlow* is a binary distribution of TensorFlow* with In…
10 …Intel&#174; Optimizations for TensorFlow* is a binary distribution of TensorFlow* with Intel&#174;…
13 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/LEGAL-NOTICE ./licenses/
14 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/LICENSE ./licenses/
15 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/third_party_programs_licen…
16 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/third_party_programs_licen…
31 # Intel Optimizations specific Envs
Dhorovod-cpu.partial.Dockerfile4 LABEL name="Intel&#174; Optimizations for TensorFlow* with Open MPI* and Horovod*" \
5 maintainer="Abolfazl Shahbazi <abolfazl.shahbazi@intel.com>" \
6 vendor="Intel&#174; Corporation" \
9 …summary="Intel&#174; Optimizations for TensorFlow* with Open MPI* and Horovod* is a binary distrib…
10 …Intel&#174; Optimizations for TensorFlow* with Open MPI* and Horovod* is a binary distribution of …
13 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/LEGAL-NOTICE ./licenses/
14 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/LICENSE ./licenses/
15 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/third_party_programs_licen…
16 ADD https://raw.githubusercontent.com/Intel-tensorflow/tensorflow/v2.7.0/third_party_programs_licen…
31 # Intel Optimizations specific Envs
/external/eigen/doc/
DUsingIntelMKL.dox2 Copyright (c) 2011, Intel Corporation. All rights reserved.
13 * Neither the name of Intel Corporation nor the names of its contributors may
29 * Content : Documentation on the use of Intel MKL through Eigen
35 /** \page TopicUsingIntelMKL Using Intel® MKL from %Eigen
37 <!-- \section TopicUsingIntelMKL_Intro Eigen and Intel® Math Kernel Library (Intel® MKL) -->
39 …ter, users can benefit from built-in Intel® Math Kernel Library (MKL) optimizations with an instal…
41 <a href="http://eigen.tuxfamily.org/Counter/redirect_to_mkl.php"> Intel MKL </a> provides highly op…
42 Intel MKL is available on Linux, Mac and Windows for both Intel64 and IA32 architectures.
45 Intel® MKL is a proprietary software and it is the responsibility of users to buy or register for c…
47 Using Intel MKL through %Eigen is easy:
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